Hex Inverters (Rev. C) - Texas Instruments - Farnell Element 14 - Revenir à l'accueil
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Farnell-2-GBPS-Diffe..> 28-Jul-2014 17:42 2.7M
Farnell-LMT88-2.4V-1..> 28-Jul-2014 17:42 2.8M
Farnell-Octal-Genera..> 28-Jul-2014 17:42 2.8M
Farnell-Dual-MOSFET-..> 28-Jul-2014 17:41 2.8M
Farnell-TLV320AIC325..> 28-Jul-2014 17:41 2.9M
Farnell-SN54LV4053A-..> 28-Jul-2014 17:20 5.9M
Farnell-TAS1020B-USB..> 28-Jul-2014 17:19 6.2M
Farnell-TPS40060-Wid..> 28-Jul-2014 17:19 6.3M
Farnell-TL082-Wide-B..> 28-Jul-2014 17:16 6.3M
Farnell-RF-short-tra..> 28-Jul-2014 17:16 6.3M
Farnell-maxim-integr..> 28-Jul-2014 17:14 6.4M
Farnell-TSV6390-TSV6..> 28-Jul-2014 17:14 6.4M
Farnell-Fast-Charge-..> 28-Jul-2014 17:12 6.4M
Farnell-NVE-datashee..> 28-Jul-2014 17:12 6.5M
Farnell-Excalibur-Hi..> 28-Jul-2014 17:10 2.4M
Farnell-Excalibur-Hi..> 28-Jul-2014 17:10 2.4M
Farnell-REF102-10V-P..> 28-Jul-2014 17:09 2.4M
Farnell-TMS320F28055..> 28-Jul-2014 17:09 2.7M
Farnell-MULTICOMP-Ra..> 22-Jul-2014 12:35 5.9M
Farnell-RASPBERRY-PI..> 22-Jul-2014 12:35 5.9M
Farnell-Dremel-Exper..> 22-Jul-2014 12:34 1.6M
Farnell-STM32F103x8-..> 22-Jul-2014 12:33 1.6M
Farnell-BD6xxx-PDF.htm 22-Jul-2014 12:33 1.6M
Farnell-L78S-STMicro..> 22-Jul-2014 12:32 1.6M
Farnell-RaspiCam-Doc..> 22-Jul-2014 12:32 1.6M
Farnell-SB520-SB5100..> 22-Jul-2014 12:32 1.6M
Farnell-iServer-Micr..> 22-Jul-2014 12:32 1.6M
Farnell-LUMINARY-MIC..> 22-Jul-2014 12:31 3.6M
Farnell-TEXAS-INSTRU..> 22-Jul-2014 12:31 2.4M
Farnell-TEXAS-INSTRU..> 22-Jul-2014 12:30 4.6M
Farnell-CLASS 1-or-2..> 22-Jul-2014 12:30 4.7M
Farnell-TEXAS-INSTRU..> 22-Jul-2014 12:29 4.8M
Farnell-Evaluating-t..> 22-Jul-2014 12:28 4.9M
Farnell-LM3S6952-Mic..> 22-Jul-2014 12:27 5.9M
Farnell-Keyboard-Mou..> 22-Jul-2014 12:27 5.9M
Farnell-Full-Datashe..> 15-Jul-2014 17:08 951K
Farnell-pmbta13_pmbt..> 15-Jul-2014 17:06 959K
Farnell-EE-SPX303N-4..> 15-Jul-2014 17:06 969K
Farnell-Datasheet-NX..> 15-Jul-2014 17:06 1.0M
Farnell-Datasheet-Fa..> 15-Jul-2014 17:05 1.0M
Farnell-MIDAS-un-tra..> 15-Jul-2014 17:05 1.0M
Farnell-SERIAL-TFT-M..> 15-Jul-2014 17:05 1.0M
Farnell-MCOC1-Farnel..> 15-Jul-2014 17:05 1.0M
Farnell-TMR-2-series..> 15-Jul-2014 16:48 787K
Farnell-DC-DC-Conver..> 15-Jul-2014 16:48 781K
Farnell-Full-Datashe..> 15-Jul-2014 16:47 803K
Farnell-TMLM-Series-..> 15-Jul-2014 16:47 810K
Farnell-TEL-5-Series..> 15-Jul-2014 16:47 814K
Farnell-TXL-series-t..> 15-Jul-2014 16:47 829K
Farnell-TEP-150WI-Se..> 15-Jul-2014 16:47 837K
Farnell-AC-DC-Power-..> 15-Jul-2014 16:47 845K
Farnell-TIS-Instruct..> 15-Jul-2014 16:47 845K
Farnell-TOS-tracopow..> 15-Jul-2014 16:47 852K
Farnell-TCL-DC-traco..> 15-Jul-2014 16:46 858K
Farnell-TIS-series-t..> 15-Jul-2014 16:46 875K
Farnell-TMR-2-Series..> 15-Jul-2014 16:46 897K
Farnell-TMR-3-WI-Ser..> 15-Jul-2014 16:46 939K
Farnell-TEN-8-WI-Ser..> 15-Jul-2014 16:46 939K
Farnell-Full-Datashe..> 15-Jul-2014 16:46 947K
Farnell-HIP4081A-Int..> 07-Jul-2014 19:47 1.0M
Farnell-ISL6251-ISL6..> 07-Jul-2014 19:47 1.1M
Farnell-DG411-DG412-..> 07-Jul-2014 19:47 1.0M
Farnell-3367-ARALDIT..> 07-Jul-2014 19:46 1.2M
Farnell-ICM7228-Inte..> 07-Jul-2014 19:46 1.1M
Farnell-Data-Sheet-K..> 07-Jul-2014 19:46 1.2M
Farnell-Silica-Gel-M..> 07-Jul-2014 19:46 1.2M
Farnell-TKC2-Dusters..> 07-Jul-2014 19:46 1.2M
Farnell-CRC-HANDCLEA..> 07-Jul-2014 19:46 1.2M
Farnell-760G-French-..> 07-Jul-2014 19:45 1.2M
Farnell-Decapant-KF-..> 07-Jul-2014 19:45 1.2M
Farnell-1734-ARALDIT..> 07-Jul-2014 19:45 1.2M
Farnell-Araldite-Fus..> 07-Jul-2014 19:45 1.2M
Farnell-fiche-de-don..> 07-Jul-2014 19:44 1.4M
Farnell-safety-data-..> 07-Jul-2014 19:44 1.4M
Farnell-A-4-Hardener..> 07-Jul-2014 19:44 1.4M
Farnell-CC-Debugger-..> 07-Jul-2014 19:44 1.5M
Farnell-MSP430-Hardw..> 07-Jul-2014 19:43 1.8M
Farnell-SmartRF06-Ev..> 07-Jul-2014 19:43 1.6M
Farnell-CC2531-USB-H..> 07-Jul-2014 19:43 1.8M
Farnell-Alimentation..> 07-Jul-2014 19:43 1.8M
Farnell-BK889B-PONT-..> 07-Jul-2014 19:42 1.8M
Farnell-User-Guide-M..> 07-Jul-2014 19:41 2.0M
Farnell-T672-3000-Se..> 07-Jul-2014 19:41 2.0M
Farnell-0050375063-D..> 18-Jul-2014 17:03 2.5M
Farnell-Mini-Fit-Jr-..> 18-Jul-2014 17:03 2.5M
Farnell-43031-0002-M..> 18-Jul-2014 17:03 2.5M
Farnell-0433751001-D..> 18-Jul-2014 17:02 2.5M
Farnell-Cube-3D-Prin..> 18-Jul-2014 17:02 2.5M
Farnell-MTX-Compact-..> 18-Jul-2014 17:01 2.5M
Farnell-MTX-3250-MTX..> 18-Jul-2014 17:01 2.5M
Farnell-ATtiny26-L-A..> 18-Jul-2014 17:00 2.6M
Farnell-MCP3421-Micr..> 18-Jul-2014 17:00 1.2M
Farnell-LM19-Texas-I..> 18-Jul-2014 17:00 1.2M
Farnell-Data-Sheet-S..> 18-Jul-2014 17:00 1.2M
Farnell-LMH6518-Texa..> 18-Jul-2014 16:59 1.3M
Farnell-AD7719-Low-V..> 18-Jul-2014 16:59 1.4M
Farnell-DAC8143-Data..> 18-Jul-2014 16:59 1.5M
Farnell-BGA7124-400-..> 18-Jul-2014 16:59 1.5M
Farnell-SICK-OPTIC-E..> 18-Jul-2014 16:58 1.5M
Farnell-LT3757-Linea..> 18-Jul-2014 16:58 1.6M
Farnell-LT1961-Linea..> 18-Jul-2014 16:58 1.6M
Farnell-PIC18F2420-2..> 18-Jul-2014 16:57 2.5M
Farnell-DS3231-DS-PD..> 18-Jul-2014 16:57 2.5M
Farnell-RDS-80-PDF.htm 18-Jul-2014 16:57 1.3M
Farnell-AD8300-Data-..> 18-Jul-2014 16:56 1.3M
Farnell-LT6233-Linea..> 18-Jul-2014 16:56 1.3M
Farnell-MAX1365-MAX1..> 18-Jul-2014 16:56 1.4M
Farnell-XPSAF5130-PD..> 18-Jul-2014 16:56 1.4M
Farnell-DP83846A-DsP..> 18-Jul-2014 16:55 1.5M
Farnell-Dremel-Exper..> 18-Jul-2014 16:55 1.6M
Farnell-MCOC1-Farnel..> 16-Jul-2014 09:04 1.0M
Farnell-SL3S1203_121..> 16-Jul-2014 09:04 1.1M
Farnell-PN512-Full-N..> 16-Jul-2014 09:03 1.4M
Farnell-SL3S4011_402..> 16-Jul-2014 09:03 1.1M
Farnell-LPC408x-7x 3..> 16-Jul-2014 09:03 1.6M
Farnell-PCF8574-PCF8..> 16-Jul-2014 09:03 1.7M
Farnell-LPC81xM-32-b..> 16-Jul-2014 09:02 2.0M
Farnell-LPC1769-68-6..> 16-Jul-2014 09:02 1.9M
Farnell-Download-dat..> 16-Jul-2014 09:02 2.2M
Farnell-LPC3220-30-4..> 16-Jul-2014 09:02 2.2M
Farnell-LPC11U3x-32-..> 16-Jul-2014 09:01 2.4M
Farnell-SL3ICS1002-1..> 16-Jul-2014 09:01 2.5M
Farnell-T672-3000-Se..> 08-Jul-2014 18:59 2.0M
Farnell-tesa®pack63..> 08-Jul-2014 18:56 2.0M
Farnell-Encodeur-USB..> 08-Jul-2014 18:56 2.0M
Farnell-CC2530ZDK-Us..> 08-Jul-2014 18:55 2.1M
Farnell-2020-Manuel-..> 08-Jul-2014 18:55 2.1M
Farnell-Synchronous-..> 08-Jul-2014 18:54 2.1M
Farnell-Arithmetic-L..> 08-Jul-2014 18:54 2.1M
Farnell-NA555-NE555-..> 08-Jul-2014 18:53 2.2M
Farnell-4-Bit-Magnit..> 08-Jul-2014 18:53 2.2M
Farnell-LM555-Timer-..> 08-Jul-2014 18:53 2.2M
Farnell-L293d-Texas-..> 08-Jul-2014 18:53 2.2M
Farnell-SN54HC244-SN..> 08-Jul-2014 18:52 2.3M
Farnell-MAX232-MAX23..> 08-Jul-2014 18:52 2.3M
Farnell-High-precisi..> 08-Jul-2014 18:51 2.3M
Farnell-SMU-Instrume..> 08-Jul-2014 18:51 2.3M
Farnell-900-Series-B..> 08-Jul-2014 18:50 2.3M
Farnell-BA-Series-Oh..> 08-Jul-2014 18:50 2.3M
Farnell-UTS-Series-S..> 08-Jul-2014 18:49 2.5M
Farnell-270-Series-O..> 08-Jul-2014 18:49 2.3M
Farnell-UTS-Series-S..> 08-Jul-2014 18:49 2.8M
Farnell-Tiva-C-Serie..> 08-Jul-2014 18:49 2.6M
Farnell-UTO-Souriau-..> 08-Jul-2014 18:48 2.8M
Farnell-Clipper-Seri..> 08-Jul-2014 18:48 2.8M
Farnell-SOURIAU-Cont..> 08-Jul-2014 18:47 3.0M
Farnell-851-Series-P..> 08-Jul-2014 18:47 3.0M
Farnell-SL59830-Inte..> 06-Jul-2014 10:07 1.0M
Farnell-ALF1210-PDF.htm 06-Jul-2014 10:06 4.0M
Farnell-AD7171-16-Bi..> 06-Jul-2014 10:06 1.0M
Farnell-Low-Noise-24..> 06-Jul-2014 10:05 1.0M
Farnell-ESCON-Featur..> 06-Jul-2014 10:05 938K
Farnell-74LCX573-Fai..> 06-Jul-2014 10:05 1.9M
Farnell-1N4148WS-Fai..> 06-Jul-2014 10:04 1.9M
Farnell-FAN6756-Fair..> 06-Jul-2014 10:04 850K
Farnell-Datasheet-Fa..> 06-Jul-2014 10:04 861K
Farnell-ES1F-ES1J-fi..> 06-Jul-2014 10:04 867K
Farnell-QRE1113-Fair..> 06-Jul-2014 10:03 879K
Farnell-2N7002DW-Fai..> 06-Jul-2014 10:03 886K
Farnell-FDC2512-Fair..> 06-Jul-2014 10:03 886K
Farnell-FDV301N-Digi..> 06-Jul-2014 10:03 886K
Farnell-S1A-Fairchil..> 06-Jul-2014 10:03 896K
Farnell-BAV99-Fairch..> 06-Jul-2014 10:03 896K
Farnell-74AC00-74ACT..> 06-Jul-2014 10:03 911K
Farnell-NaPiOn-Panas..> 06-Jul-2014 10:02 911K
Farnell-LQ-RELAYS-AL..> 06-Jul-2014 10:02 924K
Farnell-ev-relays-ae..> 06-Jul-2014 10:02 926K
Farnell-ESCON-Featur..> 06-Jul-2014 10:02 931K
Farnell-Amplifier-In..> 06-Jul-2014 10:02 940K
Farnell-Serial-File-..> 06-Jul-2014 10:02 941K
Farnell-Both-the-Del..> 06-Jul-2014 10:01 948K
Farnell-Videk-PDF.htm 06-Jul-2014 10:01 948K
Farnell-EPCOS-173438..> 04-Jul-2014 10:43 3.3M
Farnell-Sensorless-C..> 04-Jul-2014 10:42 3.3M
Farnell-197.31-KB-Te..> 04-Jul-2014 10:42 3.3M
Farnell-PIC12F609-61..> 04-Jul-2014 10:41 3.7M
Farnell-PADO-semi-au..> 04-Jul-2014 10:41 3.7M
Farnell-03-iec-runds..> 04-Jul-2014 10:40 3.7M
Farnell-ACC-Silicone..> 04-Jul-2014 10:40 3.7M
Farnell-Series-TDS10..> 04-Jul-2014 10:39 4.0M
Farnell-03-iec-runds..> 04-Jul-2014 10:40 3.7M
Farnell-0430300011-D..> 14-Jun-2014 18:13 2.0M
Farnell-06-6544-8-PD..> 26-Mar-2014 17:56 2.7M
Farnell-3M-Polyimide..> 21-Mar-2014 08:09 3.9M
Farnell-3M-VolitionT..> 25-Mar-2014 08:18 3.3M
Farnell-10BQ060-PDF.htm 14-Jun-2014 09:50 2.4M
Farnell-10TPB47M-End..> 14-Jun-2014 18:16 3.4M
Farnell-12mm-Size-In..> 14-Jun-2014 09:50 2.4M
Farnell-24AA024-24LC..> 23-Jun-2014 10:26 3.1M
Farnell-50A-High-Pow..> 20-Mar-2014 17:31 2.9M
Farnell-197.31-KB-Te..> 04-Jul-2014 10:42 3.3M
Farnell-1907-2006-PD..> 26-Mar-2014 17:56 2.7M
Farnell-5910-PDF.htm 25-Mar-2014 08:15 3.0M
Farnell-6517b-Electr..> 29-Mar-2014 11:12 3.3M
Farnell-A-True-Syste..> 29-Mar-2014 11:13 3.3M
Farnell-ACC-Silicone..> 04-Jul-2014 10:40 3.7M
Farnell-AD524-PDF.htm 20-Mar-2014 17:33 2.8M
Farnell-ADL6507-PDF.htm 14-Jun-2014 18:19 3.4M
Farnell-ADSP-21362-A..> 20-Mar-2014 17:34 2.8M
Farnell-ALF1210-PDF.htm 04-Jul-2014 10:39 4.0M
Farnell-ALF1225-12-V..> 01-Apr-2014 07:40 3.4M
Farnell-ALF2412-24-V..> 01-Apr-2014 07:39 3.4M
Farnell-AN10361-Phil..> 23-Jun-2014 10:29 2.1M
Farnell-ARADUR-HY-13..> 26-Mar-2014 17:55 2.8M
Farnell-ARALDITE-201..> 21-Mar-2014 08:12 3.7M
Farnell-ARALDITE-CW-..> 26-Mar-2014 17:56 2.7M
Farnell-ATMEL-8-bit-..> 19-Mar-2014 18:04 2.1M
Farnell-ATMEL-8-bit-..> 11-Mar-2014 07:55 2.1M
Farnell-ATmega640-VA..> 14-Jun-2014 09:49 2.5M
Farnell-ATtiny20-PDF..> 25-Mar-2014 08:19 3.6M
Farnell-ATtiny26-L-A..> 13-Jun-2014 18:40 1.8M
Farnell-Alimentation..> 14-Jun-2014 18:24 2.5M
Farnell-Alimentation..> 01-Apr-2014 07:42 3.4M
Farnell-Amplificateu..> 29-Mar-2014 11:11 3.3M
Farnell-An-Improved-..> 14-Jun-2014 09:49 2.5M
Farnell-Atmel-ATmega..> 19-Mar-2014 18:03 2.2M
Farnell-Avvertenze-e..> 14-Jun-2014 18:20 3.3M
Farnell-BC846DS-NXP-..> 13-Jun-2014 18:42 1.6M
Farnell-BC847DS-NXP-..> 23-Jun-2014 10:24 3.3M
Farnell-BF545A-BF545..> 23-Jun-2014 10:28 2.1M
Farnell-BK2650A-BK26..> 29-Mar-2014 11:10 3.3M
Farnell-BT151-650R-N..> 13-Jun-2014 18:40 1.7M
Farnell-BTA204-800C-..> 13-Jun-2014 18:42 1.6M
Farnell-BUJD203AX-NX..> 13-Jun-2014 18:41 1.7M
Farnell-BYV29F-600-N..> 13-Jun-2014 18:42 1.6M
Farnell-BYV79E-serie..> 10-Mar-2014 16:19 1.6M
Farnell-BZX384-serie..> 23-Jun-2014 10:29 2.1M
Farnell-Battery-GBA-..> 14-Jun-2014 18:13 2.0M
Farnell-C.A-6150-C.A..> 14-Jun-2014 18:24 2.5M
Farnell-C.A 8332B-C...> 01-Apr-2014 07:40 3.4M
Farnell-CC2560-Bluet..> 29-Mar-2014 11:14 2.8M
Farnell-CD4536B-Type..> 14-Jun-2014 18:13 2.0M
Farnell-CIRRUS-LOGIC..> 10-Mar-2014 17:20 2.1M
Farnell-CS5532-34-BS..> 01-Apr-2014 07:39 3.5M
Farnell-Cannon-ZD-PD..> 11-Mar-2014 08:13 2.8M
Farnell-Ceramic-tran..> 14-Jun-2014 18:19 3.4M
Farnell-Circuit-Note..> 26-Mar-2014 18:00 2.8M
Farnell-Circuit-Note..> 26-Mar-2014 18:00 2.8M
Farnell-Cles-electro..> 21-Mar-2014 08:13 3.9M
Farnell-Conception-d..> 11-Mar-2014 07:49 2.4M
Farnell-Connectors-N..> 14-Jun-2014 18:12 2.1M
Farnell-Construction..> 14-Jun-2014 18:25 2.5M
Farnell-Controle-de-..> 11-Mar-2014 08:16 2.8M
Farnell-Cordless-dri..> 14-Jun-2014 18:13 2.0M
Farnell-Current-Tran..> 26-Mar-2014 17:58 2.7M
Farnell-Current-Tran..> 26-Mar-2014 17:58 2.7M
Farnell-Current-Tran..> 26-Mar-2014 17:59 2.7M
Farnell-Current-Tran..> 26-Mar-2014 17:59 2.7M
Farnell-DC-Fan-type-..> 14-Jun-2014 09:48 2.5M
Farnell-DC-Fan-type-..> 14-Jun-2014 09:51 1.8M
Farnell-Davum-TMC-PD..> 14-Jun-2014 18:27 2.4M
Farnell-De-la-puissa..> 29-Mar-2014 11:10 3.3M
Farnell-Directive-re..> 25-Mar-2014 08:16 3.0M
Farnell-Documentatio..> 14-Jun-2014 18:26 2.5M
Farnell-Download-dat..> 13-Jun-2014 18:40 1.8M
Farnell-ECO-Series-T..> 20-Mar-2014 08:14 2.5M
Farnell-ELMA-PDF.htm 29-Mar-2014 11:13 3.3M
Farnell-EMC1182-PDF.htm 25-Mar-2014 08:17 3.0M
Farnell-EPCOS-173438..> 04-Jul-2014 10:43 3.3M
Farnell-EPCOS-Sample..> 11-Mar-2014 07:53 2.2M
Farnell-ES2333-PDF.htm 11-Mar-2014 08:14 2.8M
Farnell-Ed.081002-DA..> 19-Mar-2014 18:02 2.5M
Farnell-F28069-Picco..> 14-Jun-2014 18:14 2.0M
Farnell-F42202-PDF.htm 19-Mar-2014 18:00 2.5M
Farnell-FDS-ITW-Spra..> 14-Jun-2014 18:22 3.3M
Farnell-FICHE-DE-DON..> 10-Mar-2014 16:17 1.6M
Farnell-Fastrack-Sup..> 23-Jun-2014 10:25 3.3M
Farnell-Ferric-Chlor..> 29-Mar-2014 11:14 2.8M
Farnell-Fiche-de-don..> 14-Jun-2014 09:47 2.5M
Farnell-Fiche-de-don..> 14-Jun-2014 18:26 2.5M
Farnell-Fluke-1730-E..> 14-Jun-2014 18:23 2.5M
Farnell-GALVA-A-FROI..> 26-Mar-2014 17:56 2.7M
Farnell-GALVA-MAT-Re..> 26-Mar-2014 17:57 2.7M
Farnell-GN-RELAYS-AG..> 20-Mar-2014 08:11 2.6M
Farnell-HC49-4H-Crys..> 14-Jun-2014 18:20 3.3M
Farnell-HFE1600-Data..> 14-Jun-2014 18:22 3.3M
Farnell-HI-70300-Sol..> 14-Jun-2014 18:27 2.4M
Farnell-HUNTSMAN-Adv..> 10-Mar-2014 16:17 1.7M
Farnell-Haute-vitess..> 11-Mar-2014 08:17 2.4M
Farnell-IP4252CZ16-8..> 13-Jun-2014 18:41 1.7M
Farnell-Instructions..> 19-Mar-2014 18:01 2.5M
Farnell-KSZ8851SNL-S..> 23-Jun-2014 10:28 2.1M
Farnell-L-efficacite..> 11-Mar-2014 07:52 2.3M
Farnell-LCW-CQ7P.CC-..> 25-Mar-2014 08:19 3.2M
Farnell-LME49725-Pow..> 14-Jun-2014 09:49 2.5M
Farnell-LOCTITE-542-..> 25-Mar-2014 08:15 3.0M
Farnell-LOCTITE-3463..> 25-Mar-2014 08:19 3.0M
Farnell-LUXEON-Guide..> 11-Mar-2014 07:52 2.3M
Farnell-Leaded-Trans..> 23-Jun-2014 10:26 3.2M
Farnell-Les-derniers..> 11-Mar-2014 07:50 2.3M
Farnell-Loctite3455-..> 25-Mar-2014 08:16 3.0M
Farnell-Low-cost-Enc..> 13-Jun-2014 18:42 1.7M
Farnell-Lubrifiant-a..> 26-Mar-2014 18:00 2.7M
Farnell-MC3510-PDF.htm 25-Mar-2014 08:17 3.0M
Farnell-MC21605-PDF.htm 11-Mar-2014 08:14 2.8M
Farnell-MCF532x-7x-E..> 29-Mar-2014 11:14 2.8M
Farnell-MICREL-KSZ88..> 11-Mar-2014 07:54 2.2M
Farnell-MICROCHIP-PI..> 19-Mar-2014 18:02 2.5M
Farnell-MOLEX-39-00-..> 10-Mar-2014 17:19 1.9M
Farnell-MOLEX-43020-..> 10-Mar-2014 17:21 1.9M
Farnell-MOLEX-43160-..> 10-Mar-2014 17:21 1.9M
Farnell-MOLEX-87439-..> 10-Mar-2014 17:21 1.9M
Farnell-MPXV7002-Rev..> 20-Mar-2014 17:33 2.8M
Farnell-MX670-MX675-..> 14-Jun-2014 09:46 2.5M
Farnell-Microchip-MC..> 13-Jun-2014 18:27 1.8M
Farnell-Microship-PI..> 11-Mar-2014 07:53 2.2M
Farnell-Midas-Active..> 14-Jun-2014 18:17 3.4M
Farnell-Midas-MCCOG4..> 14-Jun-2014 18:11 2.1M
Farnell-Miniature-Ci..> 26-Mar-2014 17:55 2.8M
Farnell-Mistral-PDF.htm 14-Jun-2014 18:12 2.1M
Farnell-Molex-83421-..> 14-Jun-2014 18:17 3.4M
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Sefram-SP270.pdf-PDF..> 29-Mar-2014 11:46 464KSDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 Dependable Texas Instruments Quality and Reliability description/ordering information These devices contain six independent inverters. Copyright 2004, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1 2 3 4 5 6 7 14 13 12 11 10 9 8 1A 1Y 2A 2Y 3A 3Y GND VCC 6A 6Y 5A 5Y 4A 4Y SN5404 . . . J PACKAGE SN54LS04, SN54S04 . . . J OR W PACKAGE SN7404, SN74S04 . . . D, N, OR NS PACKAGE SN74LS04 . . . D, DB, N, OR NS PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 14 13 12 11 10 9 8 1A 2Y 2A VCC 3A 3Y 4A 1Y 6A 6Y GND 5Y 5A 4Y SN5404 . . . W PACKAGE (TOP VIEW) 3 2 1 20 19 9 10 11 12 13 4 5 6 7 8 18 17 16 15 14 6Y NC 5A NC 5Y 2A NC 2Y NC 3A SN54LS04, SN54S04 . . . FK PACKAGE (TOP VIEW) 1Y 1A NC 4Y 4A 6A 3Y GND NC NC − No internal connection VCC !" #!$% & "' &! #" #" (" " ") !" & & * +' &! # " , &" " " %+ %!&" " , %% # " " ' #&! #% - ./.010 %% # " " " " "& !%" ("* " "&' %% (" #&! #&! # " , &" " " %+ %!&" " , %% # " " ' SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING Tube SN7404N SN7404N PDIP − N Tube SN74LS04N SN74LS04N Tube SN74S04N SN74S04N Tube SN7404D 7404 Tape and reel SN7404DR SOIC − D Tube SN74LS04D LS04 0°C to 70°C Tape and reel SN74LS04DR 0 70 Tube SN74S04D S04 Tape and reel SN74S04DR Tape and reel SN7404NSR SN7404 SOP − NS Tape and reel SN74LS04NSR 74LS04 Tape and reel SN74S04NSR 74S04 SSOP − DB Tape and reel SN74LS04DBR LS04 Tube SN5404J SN5404J Tube SNJ5404J SNJ5404J CDIP − J Tube SN54LS04J SN54LS04J Tube SN54S04J SN54S04J Tube SNJ54LS04J SNJ54LS04J −55°C to 125°C Tube SNJ54S04J SNJ54S04J Tube SNJ5404W SNJ5404W CFP − W Tube SNJ54LS04W SNJ54LS04W Tube SNJ54S04W SNJ54S04W LCCC − FK Tube SNJ54LS04FK SNJ54LS04FK Tube SNJ54S04FK SNJ54S04FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each inverter) INPUT A OUTPUT Y H L L H SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 logic diagram (positive logic) 1A 2A 3A 4A 5A 6A 1Y 2Y 3Y 4Y 5Y 6Y Y = A SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 schematics (each gate) Input A VCC Output Y GND 130 Ω 1 kΩ 1.6 kΩ ’04 4 kΩ Input A VCC Output Y GND 20 kΩ 120 Ω ’LS04 8 kΩ 12 kΩ 1.5 kΩ 3 kΩ 4 kΩ Input A VCC Output Y GND 2.8 kΩ 900 Ω ’S04 50 Ω 3.5 kΩ 250 Ω 500 Ω Resistor values shown are nominal. SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI: ’04, ’S04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V ’LS04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. This are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Voltage values are with respect to network ground terminal. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN5404 SN7404 UNIT MIN NOM MAX MIN NOM MAX VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V IOH High-level output current −0.4 −0.4 mA IOL Low-level output current 16 16 mA TA Operating free-air temperature −55 125 0 70 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST SN5404 SN7404 CONDITIONS‡ UNIT MIN TYP§ MAX MIN TYP§ MAX VIK VCC = MIN, II = − 12 mA −1.5 −1.5 V VOH VCC = MIN, VIL = 0.8 V, IOH = −0.4 mA 2.4 3.4 2.4 3.4 V VOL VCC = MIN, VIH = 2 V, IOL = 16 mA 0.2 0.4 0.2 0.4 V II VCC = MAX, VI = 5.5 V 1 1 mA IIH VCC = MAX, VI = 2.4 V 40 40 μA IIL VCC = MAX, VI = 0.4 V −1.6 −1.6 mA IOS¶ VCC = MAX −20 −55 −18 −55 mA ICCH VCC = MAX, VI = 0 V 6 12 6 12 mA ICCL VCC = MAX, VI = 4.5 V 18 33 18 33 mA ‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. § All typical values are at VCC = 5 V, TA = 25°C. ¶ Not more than one output should be shorted at a time. SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1) FROM TO SN5404 PARAMETER SN7404 (INPUT) (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT tPLH A Y RL = 400 Ω, CL = 15 pF 12 22 ns tPHL 8 15 recommended operating conditions (see Note 3) SN54LS04 SN74LS04 UNIT MIN NOM MAX MIN NOM MAX VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.7 0.8 V IOH High-level output current −0.4 −0.4 mA IOL Low-level output current 4 8 mA TA Operating free-air temperature −55 125 0 70 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS† SN54LS04 SN74LS04 UNIT MIN TYP‡ MAX MIN TYP‡ MAX VIK VCC = MIN, II = − 18 mA −1.5 −1.5 V VOH VCC = MIN, VIL = MAX, IOH = −0.4 mA 2.5 3.4 2.7 3.4 V VOL VCC = MIN, VIH = 2 V IOL = 4 mA 0.25 0.4 0.4 V IOL = 8 mA 0.25 0.5 II VCC = MAX, VI = 7 V 0.1 0.1 mA IIH VCC = MAX, VI = 2.7 V 20 20 μA IIL VCC = MAX, VI = 0.4 V −0.4 −0.4 mA IOS§ VCC = MAX −20 −100 −20 −100 mA ICCH VCC = MAX, VI = 0 V 1.2 2.4 1.2 2.4 mA ICCL VCC = MAX, VI = 4.5 V 3.6 6.6 3.6 6.6 mA † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. switching characteristics, VCC = 5 V, TA = 25°C (see Figure 2) FROM TO SN54LS04 PARAMETER SN74LS04 (INPUT) (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT tPLH A Y RL = 2 kΩ, CL = 15 pF 9 15 ns tPHL 10 15 SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 recommended operating conditions (see Note 3) SN54S04 SN74S04 UNIT MIN NOM MAX MIN NOM MAX VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V IOH High-level output current −1 −1 mA IOL Low-level output current 20 20 mA TA Operating free-air temperature −55 125 0 70 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS† SN54S04 SN74S04 UNIT MIN TYP‡ MAX MIN TYP‡ MAX VIK VCC = MIN, II = − 18 mA −1.2 −1.2 V VOH VCC = MIN, VIL = 0.8 V, IOH = −1 mA 2.5 3.4 2.7 3.4 V VOL VCC = MIN, VIH = 2 V, IOL = 20 mA 0.5 0.5 V II VCC = MAX, VI = 5.5 V 1 1 mA IIH VCC = MAX, VI = 2.7 V 50 50 μA IIL VCC = MAX, VI = 0.5 V −2 −2 mA IOS§ VCC = MAX −40 −100 −40 −100 mA ICCH VCC = MAX, VI = 0 V 15 24 15 24 mA ICCL VCC = MAX, VI = 4.5 V 30 54 30 54 mA † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1) FROM TO SN54S04 PARAMETER SN74S04 (INPUT) (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT tPLH A Y RL = 280 Ω, CL = 15 pF 3 4.5 ns tPHL 3 5 tPLH A Y RL = 280 Ω, CL = 50 pF 4.5 ns tPHL 5 SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION SERIES 54/74 AND 54S/74S DEVICES tPHL tPLH tPLH tPHL LOAD CIRCUIT FOR 3-STATE OUTPUTS High-Level Pulse Low-Level Pulse VOLTAGE WAVEFORMS PULSE DURATIONS Input Out-of-Phase Output (see Note D) 3 V 0 V VOL VOH VOH VOL In-Phase Output (see Note D) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC RL Test Point From Output Under Test CL (see Note A) LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS LOAD CIRCUIT FOR 2-STATE TOTEM-POLE OUTPUTS (see Note B) VCC RL From Output Under Test CL (see Note A) Test Point (see Note B) VCC RL From Output Under Test CL (see Note A) Test Point 1 kΩ NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL. E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO≈ 50 Ω; tr and tf ≤ 7 ns for Series 54/74 devices and tr and tf ≤ 2.5 ns for Series 54S/74S devices. F. The outputs are measured one at a time, with one input transition per measurement. S1 S2 tPHZ tPZL tPLZ tPZH 3 V 3 V 0 V 0 V th tsu VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Timing Input Data Input 3 V 0 V Output Control (low-level enabling) Waveform 1 (see Notes C and D) Waveform 2 (see Notes C and D) ≈1.5 V VOH − 0.5 V VOL + 0.5 V ≈1.5 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V tw 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V VOH VOL Figure 1. Load Circuits and Voltage Waveforms SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 PARAMETER MEASUREMENT INFORMATION SERIES 54LS/74LS DEVICES tPHL tPLH tPLH tPHL LOAD CIRCUIT FOR 3-STATE OUTPUTS High-Level Pulse Low-Level Pulse VOLTAGE WAVEFORMS PULSE DURATIONS Input Out-of-Phase Output (see Note D) 3 V 0 V VOL VOH VOH VOL In-Phase Output (see Note D) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC RL Test Point From Output Under Test CL (see Note A) LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS LOAD CIRCUIT FOR 2-STATE TOTEM-POLE OUTPUTS (see Note B) VCC RL From Output Under Test CL (see Note A) Test Point (see Note B) VCC RL From Output Under Test CL (see Note A) Test Point 5 kΩ NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL. E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples. F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns, tf ≤ 2.6 ns. G. The outputs are measured one at a time, with one input transition per measurement. S1 S2 tPHZ tPZL tPLZ tPZH 3 V 3 V 0 V 0 V th tsu VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Timing Input Data Input 3 V 0 V Output Control (low-level enabling) Waveform 1 (see Notes C and D) Waveform 2 (see Notes C and D) ≈1.5 V VOH − 0.5 V VOL + 0.5 V ≈1.5 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V tw 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V VOL VOH Figure 2. Load Circuits and Voltage Waveforms PACKAGE OPTION ADDENDUM www.ti.com 2-May-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples JM38510/00105BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 00105BCA JM38510/00105BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 00105BDA JM38510/07003BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 07003BCA JM38510/07003BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 07003BDA JM38510/30003B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 30003B2A JM38510/30003BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 30003BCA JM38510/30003BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 30003BDA JM38510/30003SCA ACTIVE CDIP J 14 25 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 30003SCA JM38510/30003SDA ACTIVE CFP W 14 25 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 30003SDA M38510/00105BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 00105BCA M38510/00105BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 00105BDA M38510/07003BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 07003BCA M38510/30003B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 30003B2A M38510/30003BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 30003BCA M38510/30003BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 30003BDA M38510/30003SCA ACTIVE CDIP J 14 25 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 30003SCA M38510/30003SDA ACTIVE CFP W 14 25 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 30003SDA PACKAGE OPTION ADDENDUM www.ti.com 2-May-2014 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SN5404J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SN5404J SN54LS04J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SN54LS04J SN54S04J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SN54S04J SN7404D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 7404 SN7404DE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 7404 SN7404DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 7404 SN7404DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 7404 SN7404DRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 7404 SN7404DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 7404 SN7404N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN7404N SN7404N3 OBSOLETE PDIP N 14 TBD Call TI Call TI 0 to 70 SN7404NE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN7404N SN74LS04D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS04 SN74LS04DE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS04 SN74LS04DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS04 SN74LS04DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS04 SN74LS04DRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS04 SN74LS04DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS04 SN74LS04J OBSOLETE CDIP J 14 TBD Call TI Call TI 0 to 70 PACKAGE OPTION ADDENDUM www.ti.com 2-May-2014 Addendum-Page 3 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SN74LS04N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74LS04N SN74LS04N3 OBSOLETE PDIP N 14 TBD Call TI Call TI 0 to 70 SN74LS04NE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74LS04N SN74LS04NSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 74LS04 SN74LS04NSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 74LS04 SN74S04D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 S04 SN74S04DE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 S04 SN74S04DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 S04 SN74S04DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 S04 SN74S04DRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 S04 SN74S04DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 S04 SN74S04N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74S04N SN74S04N3 OBSOLETE PDIP N 14 TBD Call TI Call TI 0 to 70 SN74S04NE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74S04N SN74S04NSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 74S04 SN74S04NSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 74S04 SN74S04NSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 74S04 SNJ5404J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ5404J SNJ5404W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ5404W PACKAGE OPTION ADDENDUM www.ti.com 2-May-2014 Addendum-Page 4 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SNJ54LS04FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 SNJ54LS 04FK SNJ54LS04J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ54LS04J SNJ54LS04W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ54LS04W SNJ54S04FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 SNJ54S 04FK SNJ54S04J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ54S04J SNJ54S04W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ54S04W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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OTHER QUALIFIED VERSIONS OF SN5404, SN54LS04, SN54LS04-SP, SN54S04, SN7404, SN74LS04, SN74S04 : • Catalog: SN7404, SN74LS04, SN54LS04, SN74S04 • Military: SN5404, SN54LS04, SN54S04 • Space: SN54LS04-SP NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Military - QML certified for Military and Defense Applications • Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant SN7404DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74LS04DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74S04DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74S04NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN7404DR SOIC D 14 2500 367.0 367.0 38.0 SN74LS04DR SOIC D 14 2500 367.0 367.0 38.0 SN74S04DR SOIC D 14 2500 367.0 367.0 38.0 SN74S04NSR SO NS 14 2000 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2014, Texas Instruments Incorporated 1FEATURES 1 2 3 4 5 6 7 8 2IN+ 2IN– 2OUT V CC+ V CC– 1IN+ 1IN– 1OUT NE5532, NE5532A . . . D, P, OR PS PACKAGE SA5532, SA5532A . . . D OR P PACKAGE (TOP VIEW) DESCRIPTION/ORDERING INFORMATION NE5532, NE5532A SA5532, SA5532A www.ti.com................................................................................................................................................... SLOS075I–NOVEMBER 1979–REVISED APRIL 2009 DUAL LOW-NOISE OPERATIONAL AMPLIFIERS · Equivalent Input Noise Voltage: 5 nV/√Hz Typ at 1 kHz · Unity-Gain Bandwidth: 10 MHz Typ · Common-Mode Rejection Ratio: 100 dB Typ · High DC Voltage Gain: 100 V/mV Typ · Peak-to-Peak Output Voltage Swing 26 V Typ With VCC± = ±15 V and RL = 600 Ω · High Slew Rate: 9 V/ms Typ The NE5532, NE5532A, SA5532, and SA5532A are high-performance operational amplifiers combining excellent dc and ac characteristics. They feature very low noise, high output-drive capability, high unity-gain and maximum-output-swing bandwidths, low distortion, high slew rate, input-protection diodes, and output short-circuit protection. These operational amplifiers are compensated internally for unity-gain operation. These devices have specified maximum limits for equivalent input noise voltage. ORDERING INFORMATION(1) TA PACKAGE(2) ORDERABLE PART NUMBER TOP-SIDE MARKING NE5532P NE5532P PDIP – P Tube of 50 NE5532AP NE5532AP Tube of 75 NE5532D N5532 Reel of 2500 NE5532DR 0°C to 70°C SOIC – D Tube of 75 NE5532AD N5532A Reel of 2500 NE5532ADR NE5532PSR N5532 SOP – PS Reel of 2000 NE5532APSR N5532A SA5532P SA5532P PDIP – P Tube of 50 SA5532AP SA5532AP Tube of 75 SA5532D –40°C to 85°C SA5532 Reel of 2500 SA5532DR SOIC – D Tube of 75 SA5532AD SA5532A Reel of 2500 SA5532ADR (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. (2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 1979–2009, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. OUT VCC– VCC+ 36 pF 37 pF 14 pF 7 pF 15 W 460 W 15 W IN+ IN– Component values shown are nominal. ABSOLUTE MAXIMUM RATINGS(1) NE5532, NE5532A SA5532, SA5532A SLOS075I–NOVEMBER 1979–REVISED APRIL 2009................................................................................................................................................... www.ti.com SCHEMATIC (EACH AMPLIFIER) over operating free-air temperature range (unless otherwise noted) VCC+ 22 V VCC Supply voltage(2) VCC– –22 V Input voltage, either input(2) (3) VCC± Input current(4) ±10 mA Duration of output short circuit(5) Unlimited D package 97°C/W qJA Package thermal impedance(6) (7) P package 85°C/W PS package 95°C/W TJ Operating virtual-junction temperature 150°C Tstg Storage temperature range –65°C to 150°C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC–. (3) The magnitude of the input voltage must never exceed the magnitude of the supply voltage. (4) Excessive input current will flow if a differential input voltage in excess of approximately 0.6 V is applied between the inputs, unless some limiting resistance is used. (5) The output may be shorted to ground or either power supply. Temperature and/or supply voltages must be limited to ensure the maximum dissipation rating is not exceeded. (6) The package thermal impedance is calculated in accordance with JESD 51-7. (7) Maximum power dissipation is a function of TJ(max), qJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) - TA)/qJA. Operating at the absolute maximum TJ of 150°C can affect reliability. 2 Submit Documentation Feedback Copyright © 1979–2009, Texas Instruments Incorporated Product Folder Link(s): NE5532 NE5532A SA5532 SA5532A RECOMMENDED OPERATING CONDITIONS ELECTRICAL CHARACTERISTICS NE5532, NE5532A SA5532, SA5532A www.ti.com................................................................................................................................................... SLOS075I–NOVEMBER 1979–REVISED APRIL 2009 MIN MAX UNIT VCC+ Supply voltage 5 15 V VCC– Supply voltage –5 –15 V NE5532, NE5532A 0 70 TA Operating free-air temperature °C SA5532, SA5532A –40 85 VCC± = ±15 V, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS(1) MIN TYP MAX UNIT TA = 25°C 0.5 4 VIO Input offset voltage VO = 0 mV TA = Full range(2) 5 TA = 25°C 10 150 IIO Input offset current nA TA = Full range(2) 200 TA = 25°C 200 800 IIB Input bias current nA TA = Full range(2) 1000 VICR Common-mode input-voltage range ±12 ±13 V V Maximum peak-to-peak output-voltage OPP swing RL ≥ 600 Ω, VCC± = ±15 V 24 26 V TA = 25°C 15 50 RL ≥ 600 Ω, VO = ±10 V Large-signal differential-voltage TA = Full range(2) 10 AVD amplification V/mV TA = 25°C 25 100 RL ≥ 2 kΩ, VO±10 V TA = Full range(2) 15 A Small-signal differential-voltage vd amplification f = 10 kHz 2.2 V/mV BOM Maximum output-swing bandwidth RL = 600 Ω, VO = ±10 V 140 kHz B1 Unity-gain bandwidth RL = 600 Ω, CL = 100 pF 10 MHz ri Input resistance 30 300 kΩ zo Output impedance AVD = 30 dB, RL = 600 Ω, f = 10 kHz 0.3 Ω CMRR Common-mode rejection ratio VIC = VICR min 70 100 dB k Supply-voltage rejection ratio SVR (ΔV VCC± = ±9 V to ±15 V, VO = 0 80 100 dB CC±/ΔVIO) IOS Output short-circuit current 10 38 60 mA ICC Total supply curent VO = 0, No load 8 16 mA Crosstalk attenuation (VO1/VO2) V01 = 10 V peak, f = 1 kHz 110 dB (1) All characteristics are measured under open-loop conditions, with zero common-mode input voltage, unless otherwise specified. (2) Full temperature ranges are: –40°C to 85°C for the SA5532 and SA5532A, and 0°C to 70°C for the NE5532 and NE5532A. Copyright © 1979–2009, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Link(s): NE5532 NE5532A SA5532 SA5532A OPERATING CHARACTERISTICS NE5532, NE5532A SA5532, SA5532A SLOS075I–NOVEMBER 1979–REVISED APRIL 2009................................................................................................................................................... www.ti.com VCC± = ±15 V, TA = 25°C (unless otherwise noted) NE5532, SA5532 NE5532A, SA5532A PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX SR Slew rate at unity gain 9 9 V/ms Overshoot factor VI = 100 mV, RL = 600 Ω, 10 10 % AVD = 1, CL = 100 pF f = 30 Hz 8 8 10 Vn Equivalent input noise voltage nV/√Hz f = 1 kHz 5 5 6 f = 30 Hz 2.7 2.7 In Equivalent input noise current pA/√Hz f = 1 kHz 0.7 0.7 4 Submit Documentation Feedback Copyright © 1979–2009, Texas Instruments Incorporated Product Folder Link(s): NE5532 NE5532A SA5532 SA5532A PACKAGE OPTION ADDENDUM www.ti.com 17-May-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples NE5532AD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532A NE5532ADE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532A NE5532ADG4 ACTIVE SOIC D 8 TBD Call TI Call TI 0 to 70 NE5532ADR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532A NE5532ADRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532A NE5532ADRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532A NE5532AIP OBSOLETE PDIP P 8 TBD Call TI Call TI -40 to 85 NE5532AP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 NE5532AP NE5532APE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 NE5532AP NE5532APSR ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532A NE5532APSRE4 ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532A NE5532APSRG4 ACTIVE SO PS 8 TBD Call TI Call TI 0 to 70 NE5532D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532 NE5532DE4 ACTIVE SOIC D 8 TBD Call TI Call TI 0 to 70 NE5532DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532 NE5532DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 N5532 NE5532DRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532 NE5532DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532 PACKAGE OPTION ADDENDUM www.ti.com 17-May-2014 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples NE5532IP OBSOLETE PDIP P 8 TBD Call TI Call TI -40 to 85 NE5532P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 NE5532P NE5532PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 NE5532P NE5532PSR ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532 NE5532PSRE4 ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532 NE5532PSRG4 ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532 SA5532AD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA5532A SA5532ADE4 ACTIVE SOIC D 8 TBD Call TI Call TI -40 to 85 SA5532ADG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA5532A SA5532ADR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA5532A SA5532ADRE4 ACTIVE SOIC D 8 TBD Call TI Call TI -40 to 85 SA5532ADRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA5532A SA5532AP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SA5532AP SA5532APE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SA5532AP SA5532D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA5532 SA5532DE4 ACTIVE SOIC D 8 TBD Call TI Call TI -40 to 85 SA5532DG4 ACTIVE SOIC D 8 TBD Call TI Call TI -40 to 85 SA5532DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA5532 SA5532DRE4 ACTIVE SOIC D 8 TBD Call TI Call TI -40 to 85 PACKAGE OPTION ADDENDUM www.ti.com 17-May-2014 Addendum-Page 3 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SA5532DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA5532 SA5532P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SA5532P SA5532PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SA5532P (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant NE5532ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 NE5532APSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 NE5532DR SOIC D 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1 NE5532DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 NE5532DRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 NE5532PSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 SA5532ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SA5532DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 15-Oct-2013 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) NE5532ADR SOIC D 8 2500 340.5 338.1 20.6 NE5532APSR SO PS 8 2000 367.0 367.0 38.0 NE5532DR SOIC D 8 2500 364.0 364.0 27.0 NE5532DR SOIC D 8 2500 340.5 338.1 20.6 NE5532DRG4 SOIC D 8 2500 340.5 338.1 20.6 NE5532PSR SO PS 8 2000 367.0 367.0 38.0 SA5532ADR SOIC D 8 2500 340.5 338.1 20.6 SA5532DR SOIC D 8 2500 340.5 338.1 20.6 PACKAGE MATERIALS INFORMATION www.ti.com 15-Oct-2013 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2014, Texas Instruments Incorporated LM386 LM386 Low Voltage Audio Power Amplifier Literature Number: SNAS545A LM386 Low Voltage Audio Power Amplifier General Description The LM386 is a power amplifier designed for use in low voltage consumer applications. The gain is internally set to 20 to keep external part count low, but the addition of an external resistor and capacitor between pins 1 and 8 will increase the gain to any value from 20 to 200. The inputs are ground referenced while the output automatically biases to one-half the supply voltage. The quiescent power drain is only 24 milliwatts when operating from a 6 volt supply, making the LM386 ideal for battery operation. Features n Battery operation n Minimum external parts n Wide supply voltage range: 4V–12V or 5V–18V n Low quiescent current drain: 4mA n Voltage gains from 20 to 200 n Ground referenced input n Self-centering output quiescent voltage n Low distortion: 0.2% (AV = 20, VS = 6V, RL = 8W, PO = 125mW, f = 1kHz) n Available in 8 pin MSOP package Applications n AM-FM radio amplifiers n Portable tape player amplifiers n Intercoms n TV sound systems n Line drivers n Ultrasonic drivers n Small servo drivers n Power converters Equivalent Schematic and Connection Diagrams DS006976-1 Small Outline, Molded Mini Small Outline, and Dual-In-Line Packages DS006976-2 Top View Order Number LM386M-1, LM386MM-1, LM386N-1, LM386N-3 or LM386N-4 See NS Package Number M08A, MUA08A or N08E August 2000 LM386 Low Voltage Audio Power Amplifier © 2000 National Semiconductor Corporation DS006976 www.national.com Absolute Maximum Ratings (Note 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (LM386N-1, -3, LM386M-1) 15V Supply Voltage (LM386N-4) 22V Package Dissipation (Note 3) (LM386N) 1.25W (LM386M) 0.73W (LM386MM-1) 0.595W Input Voltage ±0.4V Storage Temperature −65°C to +150°C Operating Temperature 0°C to +70°C Junction Temperature +150°C Soldering Information Dual-In-Line Package Soldering (10 sec) +260°C Small Outline Package (SOIC and MSOP) Vapor Phase (60 sec) +215°C Infrared (15 sec) +220°C See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” for other methods of soldering surface mount devices. Thermal Resistance qJC (DIP) 37°C/W qJA (DIP) 107°C/W qJC (SO Package) 35°C/W qJA (SO Package) 172°C/W qJA (MSOP) 210°C/W qJC (MSOP) 56°C/W Electrical Characteristics (Notes 1, 2) TA = 25°C Parameter Conditions Min Typ Max Units Operating Supply Voltage (VS) LM386N-1, -3, LM386M-1, LM386MM-1 4 12 V LM386N-4 5 18 V Quiescent Current (IQ) VS = 6V, VIN = 0 4 8 mA Output Power (POUT) LM386N-1, LM386M-1, LM386MM-1 VS = 6V, RL = 8W, THD = 10% 250 325 mW LM386N-3 VS = 9V, RL = 8W, THD = 10% 500 700 mW LM386N-4 VS = 16V, RL = 32W, THD = 10% 700 1000 mW Voltage Gain (AV) VS = 6V, f = 1 kHz 26 dB 10 μF from Pin 1 to 8 46 dB Bandwidth (BW) VS = 6V, Pins 1 and 8 Open 300 kHz Total Harmonic Distortion (THD) VS = 6V, RL = 8W, POUT = 125 mW 0.2 % f = 1 kHz, Pins 1 and 8 Open Power Supply Rejection Ratio (PSRR) VS = 6V, f = 1 kHz, CBYPASS = 10 μF 50 dB Pins 1 and 8 Open, Referred to Output Input Resistance (RIN) 50 kW Input Bias Current (IBIAS) VS = 6V, Pins 2 and 3 Open 250 nA Note 1: All voltages are measured with respect to the ground pin, unless otherwise specified. Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit is given, however, the typical value is a good indication of device performance. Note 3: For operation in ambient temperatures above 25°C, the device must be derated based on a 150°C maximum junction temperature and 1) a thermal resistance of 107°C/W junction to ambient for the dual-in-line package and 2) a thermal resistance of 170°C/W for the small outline package. LM386 www.national.com 2 Application Hints GAIN CONTROL To make the LM386 a more versatile amplifier, two pins (1 and 8) are provided for gain control. With pins 1 and 8 open the 1.35 kW resistor sets the gain at 20 (26 dB). If a capacitor is put from pin 1 to 8, bypassing the 1.35 kW resistor, the gain will go up to 200 (46 dB). If a resistor is placed in series with the capacitor, the gain can be set to any value from 20 to 200. Gain control can also be done by capacitively coupling a resistor (or FET) from pin 1 to ground. Additional external components can be placed in parallel with the internal feedback resistors to tailor the gain and frequency response for individual applications. For example, we can compensate poor speaker bass response by frequency shaping the feedback path. This is done with a series RC from pin 1 to 5 (paralleling the internal 15 kW resistor). For 6 dB effective bass boost: R . 15 kW, the lowest value for good stable operation is R = 10 kW if pin 8 is open. If pins 1 and 8 are bypassed then R as low as 2 kW can be used. This restriction is because the amplifier is only compensated for closed-loop gains greater than 9. INPUT BIASING The schematic shows that both inputs are biased to ground with a 50 kW resistor. The base current of the input transistors is about 250 nA, so the inputs are at about 12.5 mV when left open. If the dc source resistance driving the LM386 is higher than 250 kW it will contribute very little additional offset (about 2.5 mV at the input, 50 mV at the output). If the dc source resistance is less than 10 kW, then shorting the unused input to ground will keep the offset low (about 2.5 mV at the input, 50 mV at the output). For dc source resistances between these values we can eliminate excess offset by putting a resistor from the unused input to ground, equal in value to the dc source resistance. Of course all offset problems are eliminated if the input is capacitively coupled. When using the LM386 with higher gains (bypassing the 1.35 kW resistor between pins 1 and 8) it is necessary to bypass the unused input, preventing degradation of gain and possible instabilities. This is done with a 0.1 μF capacitor or a short to ground depending on the dc source resistance on the driven input. LM386 3 www.national.com Typical Performance Characteristics Quiescent Supply Current vs Supply Voltage DS006976-5 Power Supply Rejection Ratio (Referred to the Output) vs Frequency DS006976-12 Peak-to-Peak Output Voltage Swing vs Supply Voltage DS006976-13 Voltage Gain vs Frequency DS006976-14 Distortion vs Frequency DS006976-15 Distortion vs Output Power DS006976-16 Device Dissipation vs Output Power—4W Load DS006976-17 Device Dissipation vs Output Power—8W Load DS006976-18 Device Dissipation vs Output Power—16W Load DS006976-19 LM386 www.national.com 4 Typical Applications Amplifier with Gain = 20 Minimum Parts DS006976-3 Amplifier with Gain = 200 DS006976-4 Amplifier with Gain = 50 DS006976-6 Low Distortion Power Wienbridge Oscillator DS006976-7 Amplifier with Bass Boost DS006976-8 Square Wave Oscillator DS006976-9 LM386 5 www.national.com Typical Applications (Continued) Note 4: Twist Supply lead and supply ground very tightly. Note 5: Twist speaker lead and ground very tightly. Note 6: Ferrite bead in Ferroxcube K5-001-001/3B with 3 turns of wire. Note 7: R1C1 band limits input signals. Note 8: All components must be spaced very closely to IC. Frequency Response with Bass Boost DS006976-10 AM Radio Power Amplifier DS006976-11 LM386 www.national.com 6 Physical Dimensions inches (millimeters) unless otherwise noted SO Package (M) Order Number LM386M-1 NS Package Number M08A LM386 7 www.national.com Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 8-Lead (0.118” Wide) Molded Mini Small Outline Package Order Number LM386MM-1 NS Package Number MUA08A LM386 www.national.com 8 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 www.national.com Dual-In-Line Package (N) Order Number LM386N-1, LM386N-3 or LM386N-4 NS Package Number N08E LM386 Low Voltage Audio Power Amplifier National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. 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Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Audio www.ti.com/audio Communications and Telecom www.ti.com/communications Amplifiers amplifier.ti.com Computers and Peripherals www.ti.com/computers Data Converters dataconverter.ti.com Consumer Electronics www.ti.com/consumer-apps DLP® Products www.dlp.com Energy and Lighting www.ti.com/energy DSP dsp.ti.com Industrial www.ti.com/industrial Clocks and Timers www.ti.com/clocks Medical www.ti.com/medical Interface interface.ti.com Security www.ti.com/security Logic logic.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Power Mgmt power.ti.com Transportation and Automotive www.ti.com/automotive Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Mobile Processors www.ti.com/omap Wireless Connectivity www.ti.com/wirelessconnectivity TI E2E Community Home Page e2e.ti.com Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2011, Texas Instruments Incorporated LM124, LM124A, LM224, LM224A, LM324, LM324A, LM2902, LM2902V, LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV QUADRUPLE OPERATIONAL AMPLIFIERS SLOS066T − SEPTEMBER 1975 − REVISED MARCH 2010 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 2-kV ESD Protection for: − LM224K, LM224KA − LM324K, LM324KA − LM2902K, LM2902KV, LM2902KAV Wide Supply Ranges − Single Supply . . . 3 V to 32 V (26 V for LM2902) − Dual Supplies . . . 1.5 V to 16 V (13 V for LM2902) Low Supply-Current Drain Independent of Supply Voltage . . . 0.8 mA Typ Common-Mode Input Voltage Range Includes Ground, Allowing Direct Sensing Near Ground Low Input Bias and Offset Parameters − Input Offset Voltage . . . 3 mV Typ A Versions . . . 2 mV Typ − Input Offset Current . . . 2 nA Typ − Input Bias Current . . . 20 nA Typ A Versions . . . 15 nA Typ Differential Input Voltage Range Equal to Maximum-Rated Supply Voltage . . . 32 V (26 V for LM2902) Open-Loop Differential Voltage Amplification . . . 100 V/mV Typ Internal Frequency Compensation description/ordering information These devices consist of four independent high-gain frequency-compensated operational amplifiers that are designed specifically to operate from a single supply over a wide range of voltages. Operation from split supplies also is possible if the difference between the two supplies is 3 V to 32 V (3 V to 26 V for the LM2902), and VCC is at least 1.5 V more positive than the input common-mode voltage. The low supply-current drain is independent of the magnitude of the supply voltage. Applications include transducer amplifiers, dc amplification blocks, and all the conventional operational-amplifier circuits that now can be more easily implemented in single-supply-voltage systems. For example, the LM124 can be operated directly from the standard 5-V supply that is used in digital systems and provides the required interface electronics, without requiring additional ±15-V supplies. PRODUCTION DATA information is current as of publication date. Copyright 2010, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. 1 2 3 4 5 6 7 14 13 12 11 10 9 8 1OUT 1IN− 1IN+ VCC 2IN+ 2IN− 2OUT 4OUT 4IN− 4IN+ GND 3IN+ 3IN− 3OUT LM124 . . . D, J, OR W PACKAGE LM124A . . . J OR W PACKAGE LM224, LM224A, LM224K, LM224KA . . . D OR N PACKAGE LM324, LM324K . . . D, N, NS, OR PW PACKAGE LM324A . . . D, DB, N, NS, OR PW PACKAGE LM324KA . . . D, N, NS, OR PW PACKAGE LM2902 . . . D, N, NS, OR PW PACKAGE LM2902K . . . D, DB, N, NS, OR PW PACKAGE LM2902KV, LM2902KAV . . . D OR PW PACKAGE (TOP VIEW) 3 2 1 20 19 9 10 11 12 13 4 5 6 7 8 18 17 16 15 14 4IN+ NC GND NC 3IN+ 1IN+ NC VCC NC 2IN+ LM124, LM124A . . . FK PACKAGE (TOP VIEW) 1IN− 1OUT NC 3IN− 4IN− 2IN− 2OUT NC NC − No internal connection 3OUT 4OUT On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. LM124, LM124A, LM224, LM224A, LM324, LM324A, LM2902, LM2902V, LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV QUADRUPLE OPERATIONAL AMPLIFIERS SLOS066T − SEPTEMBER 1975 − REVISED MARCH 2010 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ORDERING INFORMATION TA VIOmax AT 25°C MAX TESTED VCC PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP (N) Tube of 25 LM324N LM324N LM324KN LM324KN Tube of 50 LM324D Reel of 2500 LM324DR LM324 SOIC (D) Reel of 2500 LM324DRG3 Tube of 50 LM324KD LM324K 7 mV 30 V Reel of 2500 LM324KDR Reel of 2000 LM324NSR LM324 SOP (NS) Tube of 50 LM324KNS LM324K Reel of 2000 LM324KNSR Tube of 90 LM324PW L324 TSSOP (PW) Reel of 2000 LM324PWR Tube of 90 LM324KPW L324K 0°C to 70°C Reel of 2000 LM324KPWR PDIP (N) Tube of 25 LM324AN LM324AN Tube of 25 LM324KAN LM324KAN Tube of 50 LM324AD LM324A SOIC (D) Reel of 2500 LM324ADR Tube of 50 LM324KAD LM324KA Reel of 2500 LM324KADR 3 mV 30 V Reel of 2000 LM324ANSR LM324A SOP (NS) Tube of 50 LM324KANS LM324KA Reel of 2000 LM324KANSR SSOP (DB) Reel of 2000 LM324ADBR LM324A Tube of 90 LM324APW L324A TSSOP (PW) Reel of 2000 LM324APWR Tube of 90 LM324KAPW L324KA Reel of 2000 LM324KAPWR PDIP (N) Tube of 25 LM224N LM224N LM224KN LM224KN 5 mV 30 V Tube of 50 LM224D LM224 SOIC (D) Reel of 2500 LM224DR Tube of 50 LM224KD LM224K 25°C to 85°C Reel of 2500 LM224KDR −PDIP (N) Tube of 25 LM224AN LM224AN Tube of 25 LM224KAN LM224KAN 3 mV 30 V Tube of 50 LM224AD LM224A SOIC (D) Reel of 2500 LM224ADR Tube of 50 LM224KAD LM224KA Reel of 2500 LM224KADR † For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ‡ Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. LM124, LM124A, LM224, LM224A, LM324, LM324A, LM2902, LM2902V, LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV QUADRUPLE OPERATIONAL AMPLIFIERS SLOS066T − SEPTEMBER 1975 − REVISED MARCH 2010 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 ORDERING INFORMATION (CONTINUED) TA VIOmax AT 25°C MAX TESTED VCC PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP (N) Tube of 25 LM2902N LM2902N Tube of 25 LM2902KN LM2902KN Tube of 50 LM2902D LM2902 SOIC (D) Reel of 2500 LM2902DR Tube of 50 LM2902KD LM2902K Reel of 2500 LM2902KDR Reel of 2000 LM2902NSR LM2902 26 V SOP (NS) Tube of 50 LM2902KNS LM2902K 7 mV Reel of 2000 LM2902KNSR −40°C to 125°C SSOP (DB) Tube of 80 LM2902KDB L2902K 40 125 Reel of 2000 LM2902KDBR Tube of 90 LM2902PW L2902 TSSOP (PW) Reel of 2000 LM2902PWR Tube of 90 LM2902KPW L2902K Reel of 2000 LM2902KPWR 32 V SOIC (D) Reel of 2500 LM2902KVQDR L2902KV TSSOP (PW) Reel of 2000 LM2902KVQPWR L2902KV 2 mV 32 V SOIC (D) Reel of 2500 LM2902KAVQDR L2902KA TSSOP (PW) Reel of 2000 LM2902KAVQPWR L2902KA CDIP (J) Tube of 25 LM124J LM124J CFP (W) Tube of 25 LM124W LM124W 5 mV 30 V LCCC (FK) Tube of 55 LM124FK LM124FK 55°C to 125°C SOIC (D) Tube of 50 LM124D −LM124 Reel of 2500 LM124DR CDIP (J) Tube of 25 LM124AJ LM124AJ 2 mV 30 V CFP (W) Tube of 25 LM124AW LM124AW LCCC (FK) Tube of 55 LM124AFK LM124AFK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. symbol (each amplifier) − + IN− IN+ OUT LM124, LM124A, LM224, LM224A, LM324, LM324A, LM2902, LM2902V, LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV QUADRUPLE OPERATIONAL AMPLIFIERS SLOS066T − SEPTEMBER 1975 − REVISED MARCH 2010 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 schematic (each amplifier) To Other Amplifiers ≈6-μA Current Regulator VCC OUT GND IN− IN+ ≈100-μA Current Regulator ≈50-μA Current Regulator COMPONENT COUNT (total device) Epi-FET Transistors Diodes Resistors Capacitors 1 95 4 11 4 ≈6-μA Current Regulator † ESD protection cells - available on LM324K and LM324KA only † † LM124, LM124A, LM224, LM224A, LM324, LM324A, LM2902, LM2902V, LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV QUADRUPLE OPERATIONAL AMPLIFIERS SLOS066T − SEPTEMBER 1975 − REVISED MARCH 2010 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† LM2902 ALL OTHER DEVICES UNIT Supply voltage, VCC (see Note 1) ±13 or 26 ±16 or 32 V Differential input voltage, VID (see Note 2) ±26 ±32 V Input voltage, VI (either input) −0.3 to 26 −0.3 to 32 V Duration of output short circuit (one amplifier) to ground at (or below) TA = 25°C, VCC ≤ 15 V (see Note 3) Unlimited Unlimited D package 86 86 DB package 96 96 Package thermal impedance, θJA (see Notes 4 and 5) N package 80 80 °C/W NS package 76 76 PW package 113 113 FK package 5.61 Package thermal impedance, JC (see Notes 6 and 7) J package 15.05 °C/W W package 14.65 Operating virtual junction temperature, TJ 150 150 °C Case temperature for 60 seconds FK package 260 °C Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds J or W package 300 300 °C Storage temperature range, Tstg −65 to 150 −65 to 150 °C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values (except differential voltages and VCC specified for the measurement of IOS) are with respect to the network GND. 2. Differential voltages are at IN+, with respect to IN−. 3. Short circuits from outputs to VCC can cause excessive heating and eventual destruction. 4. Maximum power dissipation is a function of TJ(max), JA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) − TA)/JA. Operating at the absolute maximum TJ of 150°C can affect reliability. 5. The package thermal impedance is calculated in accordance with JESD 51-7. 6. Maximum power dissipation is a function of TJ(max), JC, and TC. The maximum allowable power dissipation at any allowable case temperature is PD = (TJ(max) − TC)/JC. Operating at the absolute maximum TJ of 150°C can affect reliability. 7. The package thermal impedance is calculated in accordance with MIL-STD-883. ESD protection TEST CONDITIONS TYP UNIT Human-Body Model LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV ±2 kV LM124, LM124A, LM224, LM224A, LM324, LM324A, LM2902, LM2902V, LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV QUADRUPLE OPERATIONAL AMPLIFIERS SLOS066T − SEPTEMBER 1975 − REVISED MARCH 2010 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics at specified free-air temperature, VCC = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS† TA LM124 LM224 LM324 LM324K UNIT ‡ MIN TYP§ MAX MIN TYP§ MAX V Input offset voltage VCC = 5 V to MAX, 25°C 3 5 3 7 VIO mV VIC = VICRmin, VO = 1.4 V Full range 7 9 I Input offset current V 1 4 V 25°C 2 30 2 50 IIO VO = 1.4 nA Full range 100 150 I Input bias current V 1 4 V 25°C −20 −150 −20 −250 IIB VO = 1.4 nA Full range −300 −500 25°C 0 to 0 to V Common-mode V 5 V to MAX VCC − 1.5 VCC − 1.5 VICR V input voltage range VCC = Full range 0 to 0 to VCC − 2 VCC − 2 RL = 2 kΩ 25°C VCC − 1.5 VCC − 1.5 V High-level RL = 10 kΩ 25°C VOH V output voltage V MAX RL = 2 kΩ Full range 26 26 p g VCC = RL ≥ 10 kΩ Full range 27 28 27 28 VOL Low-level output voltage RL ≤ 10 kΩ Full range 5 20 5 20 mV A Large-signal differential voltage VCC = 15 V, VO = 1 V to 11 V, 25°C 50 100 25 100 AVD V/mV amplification RL ≥ 2 kΩ Full range 25 15 CMRR Common-mode rejection ratio VIC = VICRmin 25°C 70 80 65 80 dB k Supply-voltage kSVR rejection ratio 25°C 65 100 65 100 dB (ΔVCC /ΔVIO) VO1/VO2 Crosstalk attenuation f = 1 kHz to 20 kHz 25°C 120 120 dB VCC = 15 V, V 1 V Source CC 25°C −20 −30 −60 −20 −30 −60 VID = V, VO = 0 Full range −10 −10 mA IO Output current VCC = 15 V, V 1 V Sink 25°C 10 20 10 20 O p CC VID = −V, VO = 15 V Full range 5 5 VID = −1 V, VO = 200 mV 25°C 12 30 12 30 μA IOS Short-circuit output current VCC at 5 V, GND at −5 V VO = 0, 25°C ±40 ±60 ±40 ±60 mA Supply current VO = 2.5 V, No load Full range 0.7 1.2 0.7 1.2 ICC (four amplifiers) VCC = MAX, VO = 0.5 VCC, No load Full range 1.4 3 1.4 3 mA † All characteristics are measured under open-loop conditions, with zero common-mode input voltage, unless otherwise specified. MAX VCC for testing purposes is 26 V for LM2902 and 30 V for the others. ‡ Full range is −55°C to 125°C for LM124, −25°C to 85°C for LM224, and 0°C to 70°C for LM324. § All typical values are at TA = 25°C. LM124, LM124A, LM224, LM224A, LM324, LM324A, LM2902, LM2902V, LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV QUADRUPLE OPERATIONAL AMPLIFIERS SLOS066T − SEPTEMBER 1975 − REVISED MARCH 2010 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 electrical characteristics at specified free-air temperature, VCC = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS† T ‡ LM2902 LM2902V TA UNIT MIN TYP§ MAX MIN TYP§ MAX V 5 V t Non-A-suffix 25°C 3 7 3 7 V Input offset voltage VCC = to devices Full range 10 10 VIO MAX, mV VIC = VICRmin, V 1 4 V A-suffix 25°C 1 2 IC ICR VO = 1.4 devices Full range 4 ΔVIO/ΔT Input offset voltage temperature drift RS = 0 Ω Full range 7 μV/°C I Input offset current V 1 4 V 25°C 2 50 2 50 IIO VO = 1.4 nA Full range 300 150 ΔIIO/ΔT Input offset current temperature drift Full range 10 pA/°C I Input bias current V 1 4 V 25°C −20 −250 −20 −250 IIB VO = 1.4 nA Full range −500 −500 25°C 0 to 0 to V Common-mode V 5 V to MAX VCC − 1.5 VCC − 1.5 VICR V input voltage range VCC = Full range 0 to 0 to VCC − 2 VCC − 2 RL = 2 kΩ 25°C V High-level RL = 10 kΩ 25°C VCC − 1.5 VCC − 1.5 VOH V output voltage V MAX RL = 2 kΩ Full range 22 26 p g VCC = RL ≥ 10 kΩ Full range 23 24 27 VOL Low-level output voltage RL ≤ 10 kΩ Full range 5 20 5 20 mV A Large-signal differential voltage VCC = 15 V, VO = 1 V to 11 V, 25°C 25 100 25 100 AVD V/mV amplification RL ≥ 2 kΩ Full range 15 15 CMRR Common-mode rejection ratio VIC = VICRmin 25°C 50 80 60 80 dB k Supply-voltage kSVR rejection ratio 25°C 50 100 60 100 dB (ΔVCC /ΔVIO) VO1/VO2 Crosstalk attenuation f = 1 kHz to 20 kHz 25°C 120 120 dB VCC = 15 V, V 1 V S CC 25°C −20 −30 −60 −20 −30 −60 VID = V, VO = 0 Source Full range −10 −10 mA IO Output current VCC = 15 V, V 1 V Sink 25°C 10 20 10 20 CC VID = −V, VO = 15 V Full range 5 5 VID = −1 V, VO = 200 mV 25°C 30 12 40 μA IOS Short-circuit output current VCC at 5 V, GND at −5 V VO = 0, 25°C ±40 ±60 ±40 ±60 mA Supply current VO = 2.5 V, No load Full range 0.7 1.2 0.7 1.2 ICC (four amplifiers) VCC = MAX, VO = 0.5 VCC, No load Full range 1.4 3 1.4 3 mA † All characteristics are measured under open-loop conditions, with zero common-mode input voltage, unless otherwise specified. MAX VCC for testing purposes is 26 V for LM2902 and 32 V for LM2902V. ‡ Full range is −40°C to 125°C for LM2902. § All typical values are at TA = 25°C. LM124, LM124A, LM224, LM224A, LM324, LM324A, LM2902, LM2902V, LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV QUADRUPLE OPERATIONAL AMPLIFIERS SLOS066T − SEPTEMBER 1975 − MARCH 2010 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics at specified free-air temperature, VCC = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS† TA ‡ LM124A LM224A LM324A, T LM324KA UNIT A MIN TYP§ MAX MIN TYP§ MAX MIN TYP § MAX V Input offset voltage VCC = 5 V to 30 V, 25°C 2 2 3 2 3 VIO mV VIC = VICRmin, VO = 1.4 V Full range 4 4 5 I Input offset current V 1 4 V 25°C 10 2 15 2 30 IIO VO = 1.4 nA Full range 30 30 75 I Input bias current V 1 4 V 25°C −50 −15 −80 −15 −100 IIB VO = 1.4 nA Full range −100 −100 −200 V Common-mode input V 30 V 25°C 0 to VCC − 1.5 0 to VCC − 1.5 0 to VCC − 1.5 VICR V voltage range VCC = Full range 0 to VCC − 2 0 to VCC − 2 0 to VCC − 2 RL = 2 kΩ 25°C VCC − 1.5 VCC − 1.5 VCC − 1.5 VOH High-level output voltage V 30 V High RL = 2 kΩ Full range 26 26 26 V VCC = RL ≥ 10 kΩ Full range 27 27 28 27 28 VOL Low-level output voltage RL ≤ 10 kΩ Full range 20 5 20 5 20 mV A Large-signal differential VCC = 15 V, VO = 1 V to 11 V, 25°C 50 100 50 100 25 100 AVD V/mV voltage amplification RL ≥ 2 kΩ Full range 25 25 15 CMRR Common-mode rejection ratio VIC = VICRmin 25°C 70 70 80 65 80 dB kSVR Supply-voltage rejection ratio (ΔVCC /ΔVIO) 25°C 65 65 100 65 100 dB VO1/VO2 Crosstalk attenuation f = 1 kHz to 20 kHz 25°C 120 120 120 dB VCC = 15 V, V 1 V Source 25°C −20 −20 −30 −60 −20 −30 −60 VID = V, VO = 0 Full range −10 −10 −10 mA IO Output current VCC = 15 V, V 1 V Sink 25°C 10 10 20 10 20 VID = −V, VO = 15 V Full range 5 5 5 VID = −1 V, VO = 200 mV 25°C 12 12 30 12 30 μA IOS Short-circuit output current VCC at 5 V, GND at −5 V, VO = 0 25°C ±40 ±60 ±40 ±60 ±40 ±60 mA Supply current VO = 2.5 V, No load Full range 0.7 1.2 0.7 1.2 0.7 1.2 ICC (four amplifiers) VCC = 30 V, VO = 15 V, No load Full range 1.4 3 1.4 3 1.4 3 mA † All characteristics are measured under open-loop conditions, with zero common-mode input voltage, unless otherwise specified. ‡ Full range is −55°C to 125°C for LM124A, −25°C to 85°C for LM224A, and 0°C to 70°C for LM324A. § All typical values are at TA = 25°C. LM124, LM124A, LM224, LM224A, LM324, LM324A, LM2902, LM2902V, LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV QUADRUPLE OPERATIONAL AMPLIFIERS SLOS066T − SEPTEMBER 1975 − REVISED MARCH 2010 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 operating conditions, VCC = ±15 V, TA = 25°C PARAMETER TEST CONDITIONS TYP UNIT SR Slew rate at unity gain RL = 1 MΩ, CL = 30 pF, VI = ±10 V (see Figure 1) 0.5 V/μs B1 Unity-gain bandwidth RL = 1 MΩ, CL = 20 pF (see Figure 1) 1.2 MHz Vn Equivalent input noise voltage RS = 100 Ω, VI = 0 V, f = 1 kHz (see Figure 2) 35 nV/√Hz VO − + RL CL VI VCC+ VCC− Figure 1. Unity-Gain Amplifier VO − + 100 Ω VCC+ VCC− RS 900 Ω VI = 0 V Figure 2. Noise-Test Circuit PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples 5962-7704301VCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-7704301VC A LM124JQMLV 5962-9950403V9B ACTIVE XCEPT KGD 0 100 TBD Call TI N / A for Pkg Type -55 to 125 5962-9950403VCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9950403VC A LM124AJQMLV 77043012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 77043012A LM124FKB 7704301CA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 7704301CA LM124JB 7704301DA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 7704301DA LM124WB 77043022A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 77043022A LM124AFKB 7704302CA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 7704302CA LM124AJB 7704302DA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 7704302DA LM124AWB JM38510/11005BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510 /11005BCA LM124ADR OBSOLETE SOIC D 14 TBD Call TI Call TI -55 to 125 LM124AFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 77043022A LM124AFKB LM124AJ ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 LM124AJ LM124AJB ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 7704302CA LM124AJB LM124AWB ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 7704302DA LM124AWB LM124D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 LM124 LM124DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 LM124 PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM124DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 LM124 LM124DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 LM124 LM124FKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 77043012A LM124FKB LM124J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 LM124J LM124JB ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 7704301CA LM124JB LM124N OBSOLETE PDIP N 14 TBD Call TI Call TI -55 to 125 LM124W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 LM124W LM124WB ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 7704301DA LM124WB LM224AD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224A LM224ADE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224A LM224ADG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224A LM224ADR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -25 to 85 LM224A LM224ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224A LM224ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224A LM224AN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -25 to 85 LM224AN LM224ANE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -25 to 85 LM224AN LM224D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224 LM224DE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224 LM224DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224 PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Addendum-Page 3 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM224DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -25 to 85 LM224 LM224DRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224 LM224DRG3 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -25 to 85 LM224 LM224DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224 LM224KAD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224KA LM224KADE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224KA LM224KADG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224KA LM224KADR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224KA LM224KADRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224KA LM224KADRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224KA LM224KAN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -25 to 85 LM224KAN LM224KANE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -25 to 85 LM224KAN LM224KDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224K LM224KDRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224K LM224KDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224K LM224KN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -25 to 85 LM224KN LM224KNE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -25 to 85 LM224KN LM224N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -25 to 85 LM224N PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Addendum-Page 4 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM224NE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -25 to 85 LM224N LM2902D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902 LM2902DE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902 LM2902DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902 LM2902DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 LM2902 LM2902DRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902 LM2902DRG3 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM2902 LM2902DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902 LM2902KAVQDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902KA LM2902KAVQDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902KA LM2902KAVQPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902KA LM2902KAVQPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902KA LM2902KD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902K LM2902KDB ACTIVE SSOP DB 14 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902K LM2902KDBE4 ACTIVE SSOP DB 14 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902K LM2902KDBG4 ACTIVE SSOP DB 14 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902K LM2902KDE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902K LM2902KDG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902K PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Addendum-Page 5 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM2902KDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902K LM2902KDRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902K LM2902KDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902K LM2902KN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 125 LM2902KN LM2902KNE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 125 LM2902KN LM2902KNSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902K LM2902KNSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902K LM2902KNSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902K LM2902KPW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902K LM2902KPWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902K LM2902KPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902K LM2902KPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902K LM2902KPWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902K LM2902KPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902K LM2902KVQDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902KV LM2902KVQDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902KV LM2902KVQPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902KV LM2902KVQPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902KV PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Addendum-Page 6 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM2902N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 125 LM2902N LM2902NE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 125 LM2902N LM2902NSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902 LM2902NSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902 LM2902PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902 LM2902PWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902 LM2902PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902 LM2902PWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI -40 to 125 LM2902PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 L2902 LM2902PWRE4 ACTIVE TSSOP PW 14 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902 LM2902PWRG3 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L2902 LM2902PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902 LM2902QN OBSOLETE PDIP N 14 TBD Call TI Call TI -40 to 125 LM324AD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A LM324ADBLE OBSOLETE SSOP DB 14 TBD Call TI Call TI LM324ADBR ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A LM324ADBRE4 ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A LM324ADBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A LM324ADE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Addendum-Page 7 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM324ADG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A LM324ADR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 LM324A LM324ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A LM324ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A LM324AN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 LM324AN LM324ANE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 LM324AN LM324ANSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A LM324ANSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A LM324ANSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A LM324APW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324A LM324APWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324A LM324APWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324A LM324APWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI LM324APWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 L324A LM324APWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324A LM324APWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324A LM324D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324 LM324DE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324 PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Addendum-Page 8 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM324DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324 LM324DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 LM324 LM324DRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324 LM324DRG3 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 LM324 LM324DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324 LM324KAD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324KA LM324KADE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324KA LM324KADG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324KA LM324KADR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324KA LM324KADRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324KA LM324KADRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324KA LM324KAN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 LM324KAN LM324KANE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 LM324KAN LM324KANSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324KA LM324KANSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324KA LM324KANSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324KA LM324KAPW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324KA LM324KAPWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324KA PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Addendum-Page 9 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM324KAPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324KA LM324KAPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324KA LM324KAPWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324KA LM324KAPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324KA LM324KD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324K LM324KDE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324K LM324KDG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324K LM324KDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324K LM324KDRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324K LM324KDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324K LM324KN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 LM324KN LM324KNE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 LM324KN LM324KNSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324K LM324KNSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324K LM324KNSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324K LM324KPW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324K LM324KPWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324K LM324KPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324K PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Addendum-Page 10 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM324KPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324K LM324KPWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324K LM324KPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324K LM324N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU | CU SN N / A for Pkg Type 0 to 70 LM324N LM324NE3 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU SN N / A for Pkg Type 0 to 70 LM324N LM324NE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 LM324N LM324NSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324 LM324NSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324 LM324NSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324 LM324PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324 LM324PWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324 LM324PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324 LM324PWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI 0 to 70 LM324PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 L324 LM324PWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324 LM324PWRG3 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 L324 LM324PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324 LM324Y OBSOLETE DIESALE Y 0 TBD Call TI Call TI M38510/11005BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510 /11005BCA PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Addendum-Page 11 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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OTHER QUALIFIED VERSIONS OF LM124, LM124-SP, LM124M, LM2902 : • Catalog: LM124, LM124 • Automotive: LM2902-Q1 PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Addendum-Page 12 • Enhanced Product: LM2902-EP • Military: LM124M, LM124M • Space: LM124-SP, LM124-SP NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects • Enhanced Product - Supports Defense, Aerospace and Medical Applications • Military - QML certified for Military and Defense Applications • Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant LM124DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM224ADR SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1 LM224ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM224ADRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM224ADRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM224DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM224DRG3 SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1 LM224KADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM224KDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM2902DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM2902DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM2902DRG3 SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1 LM2902DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM2902KAVQPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 LM2902KAVQPWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 LM2902KDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM2902KNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 LM2902KPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Oct-2013 Pack Materials-Page 1 Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant LM2902KVQPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 LM2902KVQPWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 LM2902NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 LM2902PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 LM2902PWRG3 TSSOP PW 14 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1 LM2902PWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 LM324ADBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 LM324ADR SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1 LM324ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM324ADRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM324ANSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 LM324APWR TSSOP PW 14 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1 LM324APWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 LM324APWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 LM324DR SOIC D 14 2500 330.0 16.4 6.55 9.05 2.1 8.0 16.0 Q1 LM324DR SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1 LM324DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM324DRG3 SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1 LM324DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM324KADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM324KANSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 LM324KAPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 LM324KDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM324KNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 LM324KPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 LM324PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 LM324PWRG3 TSSOP PW 14 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1 LM324PWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Oct-2013 Pack Materials-Page 2 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM124DR SOIC D 14 2500 367.0 367.0 38.0 LM224ADR SOIC D 14 2500 364.0 364.0 27.0 LM224ADR SOIC D 14 2500 333.2 345.9 28.6 LM224ADRG4 SOIC D 14 2500 333.2 345.9 28.6 LM224ADRG4 SOIC D 14 2500 367.0 367.0 38.0 LM224DR SOIC D 14 2500 367.0 367.0 38.0 LM224DRG3 SOIC D 14 2500 364.0 364.0 27.0 LM224KADR SOIC D 14 2500 367.0 367.0 38.0 LM224KDR SOIC D 14 2500 367.0 367.0 38.0 LM2902DR SOIC D 14 2500 333.2 345.9 28.6 LM2902DR SOIC D 14 2500 367.0 367.0 38.0 LM2902DRG3 SOIC D 14 2500 364.0 364.0 27.0 LM2902DRG4 SOIC D 14 2500 333.2 345.9 28.6 LM2902KAVQPWR TSSOP PW 14 2000 367.0 367.0 35.0 LM2902KAVQPWRG4 TSSOP PW 14 2000 367.0 367.0 35.0 LM2902KDR SOIC D 14 2500 367.0 367.0 38.0 LM2902KNSR SO NS 14 2000 367.0 367.0 38.0 LM2902KPWR TSSOP PW 14 2000 367.0 367.0 35.0 LM2902KVQPWR TSSOP PW 14 2000 367.0 367.0 35.0 LM2902KVQPWRG4 TSSOP PW 14 2000 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 23-Oct-2013 Pack Materials-Page 3 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM2902NSR SO NS 14 2000 367.0 367.0 38.0 LM2902PWR TSSOP PW 14 2000 367.0 367.0 35.0 LM2902PWRG3 TSSOP PW 14 2000 364.0 364.0 27.0 LM2902PWRG4 TSSOP PW 14 2000 367.0 367.0 35.0 LM324ADBR SSOP DB 14 2000 367.0 367.0 38.0 LM324ADR SOIC D 14 2500 364.0 364.0 27.0 LM324ADR SOIC D 14 2500 367.0 367.0 38.0 LM324ADRG4 SOIC D 14 2500 367.0 367.0 38.0 LM324ANSR SO NS 14 2000 367.0 367.0 38.0 LM324APWR TSSOP PW 14 2000 364.0 364.0 27.0 LM324APWR TSSOP PW 14 2000 367.0 367.0 35.0 LM324APWRG4 TSSOP PW 14 2000 367.0 367.0 35.0 LM324DR SOIC D 14 2500 385.0 388.0 194.0 LM324DR SOIC D 14 2500 364.0 364.0 27.0 LM324DR SOIC D 14 2500 333.2 345.9 28.6 LM324DRG3 SOIC D 14 2500 364.0 364.0 27.0 LM324DRG4 SOIC D 14 2500 333.2 345.9 28.6 LM324KADR SOIC D 14 2500 367.0 367.0 38.0 LM324KANSR SO NS 14 2000 367.0 367.0 38.0 LM324KAPWR TSSOP PW 14 2000 367.0 367.0 35.0 LM324KDR SOIC D 14 2500 367.0 367.0 38.0 LM324KNSR SO NS 14 2000 367.0 367.0 38.0 LM324KPWR TSSOP PW 14 2000 367.0 367.0 35.0 LM324PWR TSSOP PW 14 2000 367.0 367.0 35.0 LM324PWRG3 TSSOP PW 14 2000 364.0 364.0 27.0 LM324PWRG4 TSSOP PW 14 2000 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 23-Oct-2013 Pack Materials-Page 4 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01 28 PINS SHOWN Gage Plane 8,20 7,40 0,55 0,95 0,25 38 12,90 12,30 28 10,50 24 8,50 Seating Plane 7,90 9,90 30 10,50 9,90 0,38 5,60 5,00 15 0,22 14 A 28 1 16 20 6,50 6,50 14 0,05 MIN 5,90 5,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 0,15 M 0°–8° 0,10 0,09 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. 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Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2013, Texas Instruments Incorporated User's Guide SLAU295A–September 2009–Revised October 2012 TLV320AIC3254EVM-U This User’s Guide describes the operation, use, features and characteristics of the TLV320AIC3254EVMU. This small form factor evaluation module (EVM) is a programmable USB audio device that features the TLV320AIC3254 Audio Codec with miniDSP. Figure 1. TLV321AIC3254EVM-U Angle View The following related documents are available through the Texas Instruments Web site at www.ti.com. EVM-Compatible Device Data Sheets Device Literature Number TLV320AIC3254 SLAS549 TAS1020B SLES025 Contents 1 EVM Overview ............................................................................................................... 3 2 EVM Description and Basics .............................................................................................. 4 3 AIC3254EVM-U Control Software ........................................................................................ 7 Appendix A TLV320AIC3254EVM Schematic ............................................................................... 15 Appendix B TLV320AIC3254EVM Bill of Materials ......................................................................... 16 Appendix C Writing Scripts ..................................................................................................... 18 List of Figures 1 TLV321AIC3254EVM-U Angle View ..................................................................................... 1 2 Bottom and Top Views ..................................................................................................... 4 3 Default Input and Output Signals ......................................................................................... 5 4 Sounds and Audio Devices Properties................................................................................... 6 5 Main Panel Window ........................................................................................................ 8 6 Compatibility Tab............................................................................................................ 9 7 Playback Configurations and Controls.................................................................................. 10 8 Associated Script and Description ...................................................................................... 10 9 Tip Strip Example.......................................................................................................... 11 10 Status Flags Panel ........................................................................................................ 12 11 Register Tables Panel .................................................................................................... 13 SLAU295A–September 2009–Revised October 2012 TLV320AIC3254EVM-U 1 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated www.ti.com 12 Command Line interface Panel.......................................................................................... 14 List of Tables 1 TLV320AIC3254EVM Bill of Materials .................................................................................. 16 2 TLV320AIC3254EVM-U SLAU295A–September 2009–Revised October 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated www.ti.com EVM Overview 1 EVM Overview 1.1 Features • Small USB Stick form factor EVM for the TLV320AIC3254 Audio Codec. • USB connection to the PC provides power, control and streaming audio for easy evaluation. • Pre-programmed EEPROM boots the TLV320AIC3254 as a fully functional USB Audio Device when connected to a PC. • Easy to use AIC3254 Control Software (CS) configures and controls the TLV320AIC3254. The TLV320AIC3254EVM-U is a universal serial bus (USB)-based audio device for use with a personal computer running the Microsoft Windows™ XP operating system 1.2 Introduction The TLV320AIC3254EVM-U is a USB Audio Device with programmable inputs and outputs, effects and extensive routing capabilities. It is a simple platform to evaluate the TLV320AIC3254 miniDSP Audio Codec. SLAU295A–September 2009–Revised October 2012 TLV320AIC3254EVM-U 3 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated EVM Description and Basics www.ti.com 2 EVM Description and Basics This section provides information on the analog input and output, digital control, power, and general connection of the TLV320AIC3254EVM-U. 2.1 TLV320AIC3254EVM-U Hardware Description The TLV320AIC3254EVM-U has 2 stereo analog input connectors (Line-in and Mic-in) and 2 stereo analog output connectors (Line-Out and Headphone-Out) that are routed to the TLV320AIC3254. Digital audio as well as control data communicated between the PC and the EVM are interpreted by the TAS1020B USB Streaming Controller. Control data is communicated to the TLV320AIC3254 via the I2C protocol; audio data is communicated via the I2S protocol. An on-board 32KB EEPROM is capable of storing TLV320AIC3254 commands (scripts) as well as the TAS1020B firmware. A push button is provided to cycle between scripts along with an LED that provides the user feedback regarding the script that is currently loaded. The EEPROM Manager in the AIC3254 CS is used to write new scripts into the EEPROM. Figure 2. Bottom and Top Views 4 TLV320AIC3254EVM-U SLAU295A–September 2009–Revised October 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated www.ti.com EVM Description and Basics The table below summarizes the audio jacks available to connect analog inputs and outputs to the TLV320AIC3254, as well as a switch. Designator Label Associated Pin Description J1 L IN (LINE IN) IN2_L / IN2_R Line Input. External electric microphone input. J2 MIC IN (MIC IN) IN3_L / IN3_R MICBIAS is connected to both tip and ring through resistors. Line output. Only high impedance loads should J3 L OUT (LINE OUT) LOL / LOR be connected to this output (e.g. external Class-D amplifier). J4 HP OUT (HEADPHONE) HPL / HPR Headphone output. Cycles through scripts SW1 SW1 N/A loaded in the on-board EEPROM. 2.2 Getting Started Evaluation can start right out of the box. Simply connect the TLV320AIC3254EVM-U to an available USB port, connect stereo headphones to HP OUT and start playing audio with any media player. By default, when the TLV320AIC3254EVM-U is connected, the TLV320AIC3254 is automatically configured to play and record stereo audio through all four jacks, as shown below. Figure 3. Default Input and Output Signals To adjust playback volume, open “Sounds and Audio Devices” in the “Control Panel” and click the “Volume” button of the “Sound playback” section of the “Audio” tab. Ensure USB-miniEVM is selected as the default playback and recording device. SLAU295A–September 2009–Revised October 2012 TLV320AIC3254EVM-U 5 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated EVM Description and Basics www.ti.com Figure 4. Sounds and Audio Devices Properties Pressing SW1 on the EVM once will set a flat response at the outputs (LED D1 blinks once). Pressing SW1 again will switch to bass and treble boost (LED D1 blinks twice). The following section explains the software installation procedure which allows programming of the audio device. 6 TLV320AIC3254EVM-U SLAU295A–September 2009–Revised October 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated www.ti.com AIC3254EVM-U Control Software 3 AIC3254EVM-U Control Software The AIC3254 Control Software (CS) is an intuitive, easy-to-use, powerful tool to learn, evaluate, and control the TLV320AIC3254. This tool was specifically designed to make learning the TLV320AIC3254 software easy. The following sections describe the operation and installation of this software NOTE: For configuration of the codec, the TLV320AIC3254 block diagram located in SLAS549 is a good reference to help determine the signal routing. 3.1 AIC3254EVM-U CS Setup This section provides setup instructions for the AIC3254EVM-U CS. To install the AIC3254EVM-U software: 1. Download the latest version of the AIC3254EVM-U Control Software (CS) located in the TLV320AIC3254EVM-U Product Folder. 2. Open the self-extracting installation file. 3. Extract the software to a known folder. 4. Install the EVM software by double-clicking the Setup executable, and follow the directions. The user may be prompted to restart their computer. This installs all the AIC3254EVM-U software and required drivers onto the PC. SLAU295A–September 2009–Revised October 2012 TLV320AIC3254EVM-U 7 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated AIC3254EVM-U Control Software www.ti.com 3.2 AIC3254EVM-U CS Usage The following sections describe the AIC3254EVM-U CS usage. 3.2.1 Main Panel Window The Firmware Name and Version boxes provide The Main Panel window, shown in the figure below, information about the firmware loaded into the EVM's provides easy access to all the features of the EEPROM. AIC3254 CS. The USB-MODEVM Interface drop-down menu allows the user to select which communication protocol the TAS1020B USB Controller uses to communicate with the TLV320AIC3254. The TLV320AIC3254 supports I2C Standard, I2C Fast, and 8-bit register SPI. However, this EVM only supports I2C. The USB Interface selection is global to all panels, including the Command-Line Interface. The Panel Selection Tree provides access to typical configurations, features, and other panels that allow the user to control the TLV320AIC3254. The tree is divided into several categories which contain items that pop up panels. A panel can be opened by double-clicking any item inside a category in the Panel Selection Tree. Below the Panel Selection Tree are three buttons that pop up the following: • Status Flags - Allows the user to monitor the TLV320AIC3254 status flags. • Register Tables - A tool to monitor register pages. • Command-Line Interface - A tool to execute/generate scripts and monitor register activity. The USB LED indicates if the EVM is recognized by the software and the ACTIVITY LED illuminates every time a command request is sent. The dialog box at the bottom of the Main Panel provides feedback of the current status of the software. Figure 5. Main Panel Window 8 TLV320AIC3254EVM-U SLAU295A–September 2009–Revised October 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated www.ti.com AIC3254EVM-U Control Software If running the software in Windows Vista or Windows 7, right-click the AIC3254EVM-U CS shortcut and select Properties. Configure the Compatibility tab as shown in Figure 6 Figure 6. Compatibility Tab 3.2.2 Typical Configurations This category can help users to quickly become familiar with the TLV320AIC3254. Each of the panels that can be accessed through this menu have controls relevant to the selected configuration; a tab shows the script that will be loaded for that particular configuration. Each script includes a brief description of the selected configuration. SLAU295A–September 2009–Revised October 2012 TLV320AIC3254EVM-U 9 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated AIC3254EVM-U Control Software www.ti.com Figure 7. Playback Configurations and Controls Figure 8. Associated Script and Description 3.2.3 Control Categories The Digital Settings, Analog Settings, and Signal Processing categories provide control of many registers and other features of the TLV320AIC3254 . These categories are intended for the advanced user. Hovering the mouse cursor on top of a control displays a tip strip that contains page, register, and bit information. As an example, hovering on top of IN1_R of the Audio Inputs panel, as shown in Figure 9 displays p1_r55_b7-6 which means that this control writes to Page 1/Register 55/Bits D7 to D6. 10 TLV320AIC3254EVM-U SLAU295A–September 2009–Revised October 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated www.ti.com AIC3254EVM-U Control Software Figure 9. Tip Strip Example Before changing a control, see the data sheet to ensure that a particular control is compatible with the current state of the codec. As an example, some controls in the Analog Setup panel must be modified in a particular order as described in the data sheet. Other controls must only be modified with a specific hardware setup, such as powering up the AVDD LDO. All controls update their status with respect to the register contents in the following conditions: • A panel is opened. • The Execute Command Buffer button in the Command-Line Interface is pressed (if enabled). • The Refresh button at the bottom right of a panel is pressed SLAU295A–September 2009–Revised October 2012 TLV320AIC3254EVM-U 11 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated AIC3254EVM-U Control Software www.ti.com 3.2.4 Status Flags Panel The TLV320AIC3254 status flags can monitored in the Status Flags panel (Figure 10) which is located below in the Panel Selection Tree . Pressing the POLL button continuously reads all the registers relevant to each flag and updates those flags accordingly. The rate at which the registers are read can be modified by changing the value in the Polling Interval numeric control. Note that a smaller interval reduces responsiveness of other controls, especially volume sliders, due to bandwidth limitations. By default, the polling interval is 200 ms and can be set to a minimum of 20 ms. The Sticky Flags tab contains indicators whose corresponding register contents clear every time a read is performed to that register. To read all the sticky flags, click the Read Sticky Flags button. Figure 10. Status Flags Panel 12 TLV320AIC3254EVM-U SLAU295A–September 2009–Revised October 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated www.ti.com AIC3254EVM-U Control Software 3.2.5 Register Tables Panel The contents of configuration and coefficient pages of the TLV320AIC3254 can be accessed through the Register Tables panel (Figure 11). The Page Number control changes to the page to be displayed in the register table. The register table contains page information such as the register name, reset value, current value, and a bitmap of the current value. The contents of the selected page can be exported into a spreadsheet by clicking the Dump to Spreadsheet button. Figure 11. Register Tables Panel SLAU295A–September 2009–Revised October 2012 TLV320AIC3254EVM-U 13 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated AIC3254EVM-U Control Software www.ti.com 3.2.6 Command-line Interface Panel The Command-Line Interface panel provides a means to communicate with the TLV320AIC3254 using a simple scripting language (described in Appendix C). The TAS1020B USB Controller handles all communication between the PC and the TLV320AIC3254. A script is loaded into the command buffer, either by loading a script file using the File menu or by pasting text from the clipboard using the Ctrl-V key combination (Figure 12). When the command buffer is executed, the return data packets which result from each individual command are displayed in the Command History control. This control is an array (with a maximum size of 100 elements) that contains information about each command as well as status. The Interface box displays the interface used for a particular command in the Command History array. The Command box displays the type of command executed (i.e., write, read) for a particular interface. The Flag Retries box displays the number of read iterations performed by a Wait for Flag command (see Appendix C for details). The Register Data array displays the register number and data bytes that correspond to a particular command. The Information tab provides additional information related to the Command History as well as additional settings. The Syntax and Examples tabs provide useful information related to the scripting language. The File menu provides some options for working with scripts. The first option, Open Script File..., loads a command file script into the command buffer. This script can then be executed by pressing the Execute Command Buffer button. The contents of the Command Buffer can be saved using the Save Script File... option. Both the Command Buffer and Command History can be cleared by clicking their corresponding Clear buttons Figure 12. Command Line interface Panel 14 TLV320AIC3254EVM-U SLAU295A–September 2009–Revised October 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated www.ti.com Appendix A TLV320AIC3254EVM Schematic The schematic diagram for the TLV320AIC3254EVM is provided as a reference. SLAU295A–September 2009–Revised October 2012 TLV320AIC3254EVM Schematic 15 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated DOUT DIN WCLK BCLK MCLK SCLK SDA SCL RESET~ DESIGN LEAD: EDGE #: DATE: FILENAME: SCH REV: PCB REV: SHEET: OF: LEAD # DRAWN BY: PAGE INFO: TI FILENAME DATE OF BY SHEET REV REV C12 0402 0.1ufd/6.3V C16 0603 10ufd/6.3V GND TLV320AIC3254RHB U1 QFN32-RHB 25 26 27 28 29 30 31 32 6 8 4 1 2 3 5 7 16 15 14 13 12 11 10 9 21 24 22 23 19 20 18 17 C15 0805 22ufd/6.3V C11 0402 0.1ufd/6.3V GND GND GND C5 0603 0.47ufd/16V C6 0603 0.47ufd/16V GND C13 0603 .047ufd/25V C9 0603 1.0ufd/16V C14 0603 .047ufd/25V C8 0603 1.0ufd/16V GND GND GND C10 0805 22ufd/6.3V C7 0402 0.1ufd/6.3V GND GND GND C1 0603 0.47ufd/16V C2 0603 0.47ufd/16V C3 0603 10ufd/6.3V GND R4 0603 4.7K +3.3V +3.3V +3.3V J1 LEFT RIGHT Shield 2 4 1 3 6 5 J2 LEFT RIGHT Shield 2 4 1 3 6 5 J3 LEFT RIGHT Shield 2 4 1 3 6 5 J4 LEFT RIGHT Shield 2 4 1 3 6 5 C17 1210 100ufd/6.3V C18 1210 100ufd/6.3V R1 0603 1.2K R2 0603 1.2K C4 0402 0.1ufd/6.3V TLV320AIC3254RHB U1 41 40 39 38 37 36 35 34 33 QFN32-RHB GND GND GND GND GND GND GND GND GND GND C35 0603 10ufd/6.3V R3 100 0603 R5 100 0603 TLV320AIC3254_RHB_USB_EVM TLV320AIC3254_RHB_USB_EVM STEVE LEGGIO JULY 09, 2009 B B 1 4 TLV320AIC3254_RHB_USB_EVM SL LINE IN MIC IN LINE OUT HEADPHONE 6508852 SDA SCL DOUT WCLK BCLK DIN MCLK SCLK RESET~ LEAD # TI FILENAME DATE OF DRAWN BY SHEET PCB REV SCH REV BY: SHEET: OF: REV: REV: FILENAME: DATE: DESIGN LEAD: EDGE #: PAGE INFO: U2 13 14 15 17 18 19 20 22 31 30 29 27 26 25 23 24 32 34 35 36 40 39 38 37 21 8 4 28 16 33 42 41 12 11 10 9 7 6 5 45 44 43 2 1 48 3 47 46 R9 0603 1.50K C26 0603 47pfd/50v C27 0603 47pfd/50v C22 0603 1000pfd/50V 1 2 3 4 5 6 7 8 J5 TYPEA_SMT-RA NC NC CASE CASE Data+ GND +5V Data- R12 0603 100K C30 0603 1.0ufd/16V C28 0402 0.1ufd/6.3V C25 0402 0.1ufd/6.3V C29 0402 0.1ufd/6.3V C24 0402 0.1ufd/6.3V D1 0805 Yellow C23 0805 100pfd/50V C19 0402 0.1ufd/6.3V +3.3V GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +5V +5V +3.3V GND GND GND GND C33 0603 0.1ufd/50V C34 0805 10ufd/16V C32 0805 10ufd/16V 1 2 3 4 Y1 SMT-8002 6MHz/3.3V Vcc OUT OE GND GND +3.3V 1 2 SW1 GND C31 0603 0.1ufd/50V R14 0603 10K +3.3V GND +5V VR1 5 3 2 1 SOT230DBV5 3.3V/400mA 4 1 2 3 4 5 6 7 8 U3 MSOP8-DGK R13 0603 649 R8 0603 30.9K R10 0603 27.4 R11 0603 27.4 R6 0603 2.7K/5% R7 0603 2.7K/5% EEPROM USB INPUT +5.0V USB INPUT +3.3V OUTPUT POWER SUPPLY TLV320AIC3254_RHB_USB_EVM SL 2 4 B B JULY 09, 2009 STEVE LEGGIO TLV320AIC3254_RHB_USB_EVM TLV320AIC3254_RHB_USB_EVM GPIO 6508852 www.ti.com Appendix B TLV320AIC3254EVM Bill of Materials The complete bill of materials for the TLV320AIC3254EVM is provided as a reference. Table 1. TLV320AIC3254EVM Bill of Materials PCB Qty Value Ref Des Description Vendor Part number 1 U1 ULTRA LO PWR ST AUDIO CODEC Texas TLV320AIC3254 W/EMBEDDED MINI DSP QFN32- Instruments RHB RHB ROHS RESISTORS Qty Value Ref Des Description Vendor Part number 1 1.5k R9 RESISTOR SMD0603 1.50K OHM DIGI-KEY P1.50KHCT 1% THICK FILM 1/10W ROHS 3 100k R3,R5,R12 RESISTOR SMD0603 100K OHM 1% DIGI-KEY P100KHCT THICK FILM 1/10W ROHS 1 1.7k R4 RESISTOR SMD0603 4.7K OHMS DIGI-KEY P4.7KGCT 1% 1/10W ROHS 1 10k R14 RESISTOR SMD0603 10K 5% 1/10W DIGI-KEY P10KGCT ROHS 2 1.2k R1,R2 RESISTOR SMD0603 1.2K OHMS DIGI-KEY P1.2KGCT 5% 1/10W ROHS 1 649 R13 RESISTOR SMD0603 THICK FILM DIGI-KEY 311-649HRCT 649 OHMS 1% 1/10W ROHS 1 30.9k R8 RESISTOR SMD0603 30.9K OHMS 541-30.9KHCT 1% 1/10W ROHS 2 27.4k R10,R11 RESISTOR SMD0603 27.4 OHMS DIGI-KEY P27.4HCT 1% 1/10W ROHS 2 2.7k R6,R7 RESISTOR SMD0603 2.7K OHMS DIGI-KEY P2.7KGCT 5% 1/10W ROHS 2 100 R3,R5 RESISTOR SMD0603 100 OHM DIGI-KEY 541-100HCT 1/10W 1% ROHS CAPACITORS Qty Value Ref Des Description Vendor Part number 9 0.1μF C4,C7,C11,C12,C19,C24,C25,C28,C29 CAP SMD0402 CERM 0.1UFD 6.3V DIGI-KEY 445-1266-1 10% X5R ROHS 3 10μF C3,C16, C35 CAP SMD0603 CERM 10UFD 6.3V DIGI-KEY PCC2395CT 20% X5R ROHS 2 22μF C10,C15 CAP SMD0805 CERM 22UFD 6.3V DIGI-KEY 445-1422-1 20% X5R ROHS 2 47pF C26,C27 CAP SMD0603 CERM 47PFD 50V DIGI-KEY PCC470ACVCT 5% NPO ROHS 1 1000pF C22 CAP SMD0603 CERM 1000PFD 50V DIGI-KEY 445-1293-1 5% COG ROHS 1 1μF C30 CAP SMD0603 CERM 1.0UFD 16V DIGI-KEY 445-1604-1 5% X7R ROHS 4 0.47μF C1,C2,C5,C6 CAP SMD0603 CERM 0.47UFD 16V DIGI-KEY 478-1248-1 10% X5R ROHS 2 0.47μF C13,C14 CAP SMD0603 CERM 0.47UFD 25V DIGI-KEY PCC1771CT 10% X7R ROHS 2 1μF C8,C9 CAP SMD0603 CERM 1.0UFD 16V DIGI-KEY PCC2224CT 10% X5R ROHS 1 100pF C23 CAP SMD0805 CERM 100PFD 50V DIGI-KEY 490-1615-1 5% C0G ROHS 2 0.1μF C31,C33 CAP SMD0603 CERM 0.1UFD 50V DIGI-KEY 445-1314-1 10% X7R ROHS 16 TLV320AIC3254EVM Bill of Materials SLAU295A–September 2009–Revised October 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated www.ti.com Appendix B Table 1. TLV320AIC3254EVM Bill of Materials (continued) 2 10μF C32,C34 CAP SMD0805 CERM 10UFD 16V DIGI-KEY 490-3886-1 10% X5R ROHS 2 100μF C17,C18 CAP SMD1210 CERM 100UFD 6.3V DIGI-KEY 490-3390-1 20% X5R ROHS INTEGRATED CIRCUITS Qty Value Ref Des Description Vendor Part number 1 U2 USB STREAMING CONTROLLER DIGI-KEY 296-13041-5 TQFP48-PFB ROHS 1 VR1 VOLT REG 3.3V 400MA LDO CAP- DIGI-KEY 296-15819-1 FREE NMOS SOT23-DBV5 ROHS 1 U3 256K I2C SERIAL EEPROM,MSOP-8 DIGI-KEY 24AA256-I/MSND 1 D1 LED, YELLOW 2.0V SMD0805 DIGI-KEY 67-1554-1 ROHS 1 Y1 OSCILLATOR SMT 6MHz 3.3V OUT- DIGI-KEY 788- ENABLE ROHS 8002AI133E- 6.0T MISCELLANEOUS ITEMS Qty Value Ref Des Description Vendor Part number 1 J5 JACK-USB MALE TYPEA SMT-RA DIGI-KEY WM17118 4PIN ROHS J 4 J1,J2,J3,J4 ACK AUDIO MINI(3.5MM ,4-COND DIGI-KEY CP-43516SJCT PCB-RA ROHS 1 SW1 SWITCH, MOM, 160G SMT 4X3MM DIGI-KEY EG4344CT ROHS ATTENTION: All components must be Rhos compliant. Some part numbers may be either leaded or Rhos. Verify that purchased components are Rhos compliant. SLAU295A–September 2009–Revised October 2012 TLV320AIC3254EVM Bill of Materials 17 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated www.ti.com Appendix C Writing Scripts A script is simply a text file that contains data to send to the serial control buses. Each line in a script file is one command. No provision is made for extending lines beyond one line, except for the > command. A line is terminated by a carriage return. The first character of a line is the command. Commands are: I Set interface bus to use r Read from the serial control bus w Write to the serial control bus > Extend repeated write commands to lines below a w # Comment b Break d Delay f Wait for Flag The first command, I, sets the interface to use for the commands to follow. This command must be followed by one of the following parameters: i2cstd Standard mode I2C bus i2cfast Fast mode I2C bus spi8 SPI bus with 8-bit register addressing spi16 SPI bus with 16-bit register addressing For example, if a fast mode I2C bus is to be used, the script begins with: I i2cfast A double quoted string of characters following the b command can be added to provide information to the user about each breakpoint. When the script is executed, the software's command handler halts as soon as a breakpoint is detected and displays the string of characters within the double quotes. The Wait for Flag command, f, reads a specified register and verifies if the bitmap provided with the command matches the data being read. If the data does not match, the command handler retries for up to 200 times. This feature is useful when switching buffers in parts that support the adaptive filtering mode. The command f syntax follows: f [i2c address] [register] [D7][D6][D5][D4][D3][D2][D1][D0] where 'i2c address' and 'register' are in hexadecimal format and 'D7' through 'D0' are in binary format with values of 0, 1 or X for don't care. Anything following a comment command # is ignored by the parser, provided that it is on the same line. The delay command d allows the user to specify a time, in milliseconds, that the script pauses before proceeding. The delay time is entered in decimal format. A series of byte values follows either a read or write command. Each byte value is expressed in hexadecimal, and each byte must be separated by a space. Commands are interpreted and sent to the TAS1020B by the program. The first byte following an r (read) or w (write) command is the I2C slave address of the device (if I2C is used) or the first data byte to write (if SPI is usednote that SPI interfaces are not standardized on protocols, so the meaning of this byte varies with the device being addressed on the SPI bus). The second byte is the starting register address that data will be written to (again, with I2C; SPI varies. Following these two bytes are data, if writing; if reading, the third byte value is the number of bytes to read, (expressed in hexadecimal). 18 Writing Scripts SLAU295A–September 2009–Revised October 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated www.ti.com Appendix C For example, to write the values 0xAA 0x55 to an I2C device with a slave address of 0x30, starting at a register address of 0x03, the user writes: #example script I i2cfast w 30 03 AA 55 r 30 03 02 This script begins with a comment, specifies that a fast I2C bus will be used, then writes 0xAA 0x55 to the I2C slave device at address 0x30, writing the values into registers 0x03 and 0x04. The script then reads back two bytes from the same device starting at register address 0x03. Note that the slave device value does not change. It is unnecessary to set the R/W bit for I2C devices in the script; the read or write commands does that. If extensive repeated write commands are sent and commenting is desired for a group of bytes, the > command can be used to extend the bytes to other lines that follow. A usage example for the > command follows: #example script for '>' command I i2cfast # Write AA and BB to registers 3 and 4, respectively w 30 03 AA BB # Write CC, DD, EE and FF to registers 5, 6, 7 and 8, respectively > CC DD EE FF # Place a commented breakpoint b "AA BB CC DD EE FF was written, starting at register 3" # Read back all six registers, starting at register 3 r 30 03 06 The following example demonstrates usage of the Wait for Flag command, f: #example script for 'wait for flag' command I i2cfast # Switch to Page 44 w 30 00 2C # Switch buffers w 30 01 05 # Wait for bit D0 to clear. 'x' denotes a don't care. f 30 01 xxxxxxx0 Any text editor can be used to write these scripts; Jedit is an editor that is highly recommended for general usage. For more information, go to: http://www.jedit.org. Once the script is written, it can be used in the command window by running the program, and then selecting Open Script File... from the File menu. Locate the script and open it. The script is then displayed in the command buffer. The user can also edit the script once it is in the buffer and save it by selecting Save Script File... from the File menu. SLAU295A–September 2009–Revised October 2012 Writing Scripts 19 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Appendix C www.ti.com Once the script is in the command buffer, it can be executed by pressing the Execute Command Buffer button. If there are breakpoints in the script, the script executes to that point, and the user is presented with a dialog box with a button to press to continue executing the script. When ready to proceed, push that button and the script continues. 20 Writing Scripts SLAU295A–September 2009–Revised October 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated EVALUATION BOARD/KIT IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have electronics training and observe good engineering practice standards. As such, the goods being provided are not intended to be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety and environmental measures typically found in end products that incorporate such semiconductor components or circuit boards. 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Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2012, Texas Instruments Incorporated SLLS025A − JULY 1986 Copyright 1986, Texas Instruments Incorporated Revision Information POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3−1 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 • Dual Circuits Capable of Driving High-Capacitance Loads at High Speeds • Output Supply Voltage Range up to 24 V • Low Standby Power Dissipation description The SN75372 is a dual NAND gate interface circuit designed to drive power MOSFETs from TTL inputs. It provides high current and voltage levels necessary to drive large capacitive loads at high speeds. The device operates from a VCC1 of 5 V and a VCC2 of up to 24 V. The SN75372 is characterized for operation from 0°C to 70°C. schematic (each driver) VCC1 VCC2 To Other Driver To Other Driver Output Y GND Input A Enable E 1Y 7 2Y 6 E 2 EN 1A 1 2A 3 logic symbol† TTL/MOS 1 2 3 4 8 7 6 5 1A E 2A GND VCC1 1Y 2Y VCC2 D OR P PACKAGE (TOP VIEW) † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. !"# $"%&! ' #( '"! ! $#!! $# )# # #* " # ' ' + ,( '"! $!# - '# #!# &, !&"'# # - && $ # # ( SLLS025A − JULY 1986 3−2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC1 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Supply voltage range, VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 25 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Peak output current, VO (tw < 10 ms, duty cycle < 50%) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Voltage values are with respect to network GND. DISSIPATION RATING TABLE PACKAGE TA = 25°C DERATING FACTOR TA = 70°C 25 POWER RATING ABOVE TA = 25°C 70 POWER RATING D 725 mW 5.8 mW/°C 464 mW P 1000 mW 8.0 mW/°C 640 mW recommended operating conditions MIN NOM MAX UNIT Supply voltage, VCC1 4.75 5 5.25 V Supply voltage, VCC2 4.75 20 24 V High-level input voltage, VIH 2 V Low-level input voltage, VIL 0.8 V High-level output current, IOH −10 mA Low-level output current, IOL 40 mA Operating free-air temperature, TA 0 70 °C SLLS025A − JULY 1986 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3−3 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 electrical characteristics over recommended ranges of VCC1, VCC2, and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VIK Input clamp voltage II = − 12 mA −1.5 V VOH High-level output voltage VIL = 0.8 V, IOH = −50 μA VCC2−1.3 VCC2−0.8 V VIL = 0.8 V, IOH = − 10 mA VCC2−2.5 VCC2−1.8 VIH = 2 V, IOL = 10 mA 0.15 0.3 VOL Low-level output voltage VCC2 = 15 V to 24 V, IOL = 40 mA VIH = 2 V, 0.25 0.5 V VF Output clamp-diode forward voltage VI = 0, IF = 20 mA 1.5 V II Input current at maximum input VI = 5.5 V 1 mA voltage IIH High-level input current Any A VI = 2.4 V 40 A Any E 80 μA IIL Low-level input current Any A VI = 0.4 V −1 −1.6 mA Any E −2 −3.2 ICC1(H) Supply current from VCC1, both outputs high 2 4 mA ICC2(H) Supply current from VCC2, both outputs high VCC1 = 5.25 V, All inputs at 0 V, VCC2 = 24 V, No load 0.5 mA ICC1(L) Supply current from VCC1, both outputs low 16 24 mA ICC2(L) Supply current from VCC2, both outputs low VCC1 = 5.25 V, All inputs at 5 V, VCC2 = 24 V, No load 7 13 mA ICC2(S) Supply current from VCC2, standby condition VCC1 = 0, All inputs at 5 V, VCC2 = 24 V, No load 0.5 mA † All typical values are at VCC1 = 5 V, VCC2 = 20 V, and TA = 25°C. switching characteristics, VCC1 = 5 V, VCC2 = 20 V, TA = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tDLH Delay time, low-to-high-level output 20 35 ns tDHL Delay time, high-to-low-level output 10 20 ns tTLH Transition time, low-to-high-level output CL = 390 pF, RD = 10 Ω, See Figure 1 20 30 ns tTHL Transition time, high-to-low-level output 20 30 ns tPLH Propagation delay time, low-to-high-level output 10 40 65 ns tPHL Propagation delay time, high-to-low-level output 10 30 50 ns SLLS025A − JULY 1986 3−4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 PARAMETER MEASUREMENT INFORMATION 10% 5 V 2.4 V VCC1 TEST CIRCUIT Input GND VCC2 Pulse Generator (see Note A) Output CL = 390 pF (see Note B) 20 V RD Input Output VOLTAGE WAVEFORMS ≤ 10 ns 90% 1.5 V 0.5 μs tDHL tTLH VCC2−3 V 2 V 0 V VOH ≤ 10 ns 90% 1.5 V 10% tPHL tPHL tDLH tTHL VCC2−3 V 2 V VOL 3 V NOTES: A. The pulse generator has the following characteristics: PRR = 1 MHz, ZO ≈ 50 Ω. B. CL includes probe and jig capacitance. Figure 1. Test Circuit and Voltage Waveforms, Each Driver TYPICAL CHARACTERISTICS −1 HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT −10 −100 0.3 0.2 0.1 0 0 20 40 60 0.4 LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 0.5 80 100 VCC2−0.5 VCC2−1 VCC2−1.5 VCC2−2 VCC2−2.5 VCC2−3 VCC1 = 5 V VCC2 = 20 V VI = 0.8 V TA = 25°C TA = 70°C TA = 0°C VVO0HH − High-Level Output Voltage − V IOL − Low-Level Output Current − mA VCC1 = 5 V VCC2 = 20 V VI = 2 V TA = 70°C TA = 0°C VVOOLL − Low-Level Output Voltage − V IOH − High-Level Output Current − mA VCC2 − 0.01 − 0.1 Figure 2 Figure 3 SLLS025A − JULY 1986 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3−5 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 TYPICAL CHARACTERISTICS 10 20 40 100 400 1000 f − Frequency − kHz POWER DISSIPATION (BOTH DRIVERS) vs FREQUENCY 200 400 200 0 800 1000 1200 12 600 8 4 0 0 0.5 1 1.5 16 20 VOLTAGE TRANSFER CHARACTERISTICS 24 2 2.5 VI − Input Voltage − V VVO) − Output Voltage − V VCC1 = 5 V VCC2 = 20 V No Load TA = 25°C VCC1 = 5 V VCC2 = 20 V Input: 3-V Square Wave 50% Duty Cycle TA = 25°C CL = 600 pF CL = 1000 pF CL = 2000 pF CL = 4000 pF CL = 400 pF PPDT − Power Dissipation − mW Allowable in P Package Only Figure 4 Figure 5 PROPAGATION DELAY TIME, HIGH-TO-LOW-LEVEL OUTPUT vs FREE-AIR TEMPERATURE PROPAGATION DELAY TIME, LOW-TO-HIGH-LEVEL OUTPUT vs FREE-AIR TEMPERATURE 100 80 20 0 0 10 20 30 40 50 60 High-to-Low-Level Output − ns 140 180 200 70 80 60 160 120 40 TA − Free-Air Temperature − °C tkPSLVHR − Propagation Delay Time, Low-to-High-Level Output − ns ktSPVHRL − Propagation Delay Time, TA − Free-Air Temperature − °C 100 80 20 0 140 180 200 60 160 120 40 0 10 20 30 40 50 60 70 80 CL = 50 pF CL = 200 pF CL = 1000 pF CL = 2000 pF CL = 4000 pF VCC1 = 5 V VCC2 = 20 V RD = 10 Ω See Figure 1 CL = 4000 pF CL = 2000 pF CL = 1000 pF VCC1 = 5 V VCC2 = 20 V RD = 10 Ω See Figure 1 CL = 200 pF CL = 390 pF CL = 50 pF CL = 390 pF Figure 6 Figure 7 SLLS025A − JULY 1986 3−6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 TYPICAL CHARACTERISTICS 0 5 10 15 PROPAGATION DELAY TIME, LOW-TO-HIGH-LEVEL OUTPUT vs VCC2 SUPPLY VOLTAGE 20 25 100 80 20 0 140 180 200 60 160 120 40 Low-to-High-Level Output − ns VCC2 − Supply Voltage − V PROPAGATION DELAY TIME, HIGH-TO-LOW-LEVEL OUTPUT vs VCC2 SUPPLY VOLTAGE 100 80 20 0 140 180 200 60 160 120 40 0 5 10 15 20 25 VCC2 − Supply Voltage − V tPLH − Propagation Delay Time, VCC1 = 5 V RD = 10 Ω TA = 25°C See Figure 1 CL = 2000 pF CL = 1000 pF CL = 200 pF CL = 390 pF CL = 50 pF VCC1 = 5 V RD = 10 Ω TA = 25°C See Figure 1 CL = 4000 pF CL = 2000 pF CL = 1000 pF CL = 390 pF CL = 200 pF CL = 50 pF CL = 4000 pF High-to-Low-Level Output − ns tPLH − Propagation Delay Time, Figure 8 Figure 9 0 1000 2000 3000 4000 VCC1 = 5 V VCC2 = 20 V TA = 25°C See Figure 1 Low-to-High-Level Output − ns 100 80 20 0 140 180 200 60 160 120 40 PROPAGATION DELAY TIME, LOW-TO-HIGH-LEVEL OUTPUT vs LOAD CAPACITANCE CL − Load Capacitance − pF RD = 10 Ω RD = 0 RD = 24 Ω 100 80 20 0 140 180 200 60 160 120 40 0 1000 2000 3000 4000 CL − Load Capacitance − pF VCC1 = 5 V VCC2 = 20 V TA = 25°C See Figure 1 RD = 24 Ω RD = 10 Ω PROPAGATION DELAY TIME, HIGH-TO-LOW-LEVEL OUTPUT vs LOAD CAPACITANCE RD = 0 ktSPVLRH − Propagation Delay Time, High-to-Low-Level Output − ns ktSPVLRH − Propagation Delay Time, Figure 10 Figure 11 NOTE: For RD = 0, operation with CL > 2000 pF violates absolute maximum current rating. SLLS025A − JULY 1986 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3−7 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 THERMAL INFORMATION power dissipation precautions Significant power may be dissipated in the SN75372 driver when charging and discharging high-capacitance loads over a wide voltage range at high frequencies. Figure 5 shows the power dissipated in a typical SN75372 as a function of load capacitance and frequency. Average power dissipated by this driver is derived from the equation PT(AV) = PDC(AV) + PC(AV) = PS(AV) where PDC(AV) is the steady-state power dissipation with the output high or low, PC(AV) is the power level during charging or discharging of the load capacitance, and PS(AV) is the power dissipation during switching between the low and high levels. None of these include energy transferred to the load, and all are averaged over a full cycle. The power components per driver channel are PC(AV) C V2 C f tHL tLH tH tL T = 1/f where the times are as defined in Figure 14. Figure 12. Output Voltage Waveform PDC(AV) = PHtH + PLtL T PS(AV) = PLHtLH + PHLtHL T PL, PH, PLH, and PHL are the respective instantaneous levels of power dissipation, C is the load capacitance. VC is the voltage across the load capacitance during the charge cycle shown by the equation VC = VOH − VOL PS(AV) may be ignored for power calculations at low frequencies. In the following power calculation, both channels are operating under identical conditions: VOH =19.2 V and VOL = 0.15 V with VCC1 = 5 V, VCC2 = 20 V, VC = 19.05 V, C = 1000 pF, and the duty cycle = 60%. At 0.5 MHz, PS(AV) is negligible and can be ignored. When the output voltage is high, ICC2 is negligible and can be ignored. On a per-channel basis using data sheet values, PDC(AV) (5 V) 2 mA 2 (20 V) 0 mA 2 (0.6)(5 V) 16 mA 2 (20 V) 7 mA 2 (0.4) PDC(AV) = 47 mW per channel Power during the charging time of the load capacitance is PC(AV) = (1000 pF) (19.05 V)2 (0.5 MHz) = 182 mW per channel Total power for each driver is PT(AV) = 47 mW + 182 mW = 229 mW and total package power is PT(AV) = (229) (2) = 458 mW. SLLS025A − JULY 1986 3−8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 APPLICATION INFORMATION driving power MOSFETs The drive requirements of power MOSFETs are much lower than comparable bipolar power transistors. The input impedance of a FET consists of a reverse biased PN junction that can be described as a large capacitance in parallel with a very high resistance. For this reason, the commonly used open-collector driver with a pullup resistor is not satisfactory for high-speed applications. In Figure 12(a), an IRF151 power MOSFET switching an inductive load is driven by an open-collector transistor driver with a 470-Ω pullup resistor. The input capacitance (Ciss) specification for an IRF151 is 4000 pF maximum. The resulting long turn-on time due to the combination of Ciss and the pullup resistor is shown in Figure 12(b). 5 V 7 4 8 3 5 2 1 6 VVO0HH − − Gate Voltage − V TLC555P 1/2 SN75447 470 Ω 48 V M VOL t − Time − μs (b) (a) IRF151 4 3 2 1 0 0 0.5 1 1.5 2 2.5 3 Figure 13. Power MOSFET Drive Using SN75447 SLLS025A − JULY 1986 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3−9 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 APPLICATION INFORMATION A faster, more efficient drive circuit uses an active pullup as well as an active pulldown output configuration, referred to as a totem-pole output. The SN75372 driver provides the high speed, totem-pole drive desired in an application of this type, see Figure 13(a). The resulting faster switching speeds are shown in Figure 13(b). 5 V TLC555P 1/2 SN75372 M t − Time − μs (b) (a) IRF151 48 V 4 3 2 1 0 0 0.5 1 1.5 2 2.5 3 VVO0HH − VVOOLL − Gate Voltage − V 7 4 8 3 5 2 1 6 Figure 14. Power MOSFET Drive Using SN75372 Power MOSFET drivers must be capable of supplying high peak currents to achieve fast switching speeds as shown by the equation Ipk VC tr where C is the capacitive load, and tr is the desired drive time. V is the voltage that the capacitance is charged to. In the circuit shown in Figure 13(a), V is found by the equation V = VOH − VOL Peak current required to maintain a rise time of 100 ns in the circuit of Figure 13(a) is IPK (30)4(109) 100(109) 120 mA Circuit capacitance can be ignored because it is very small compared to the input capacitance of the IRF151. With a VCC of 5 V, and assuming worst-cast conditions, the gate drive voltage is 3 V. For applications in which the full voltage of VCC2 must be supplied to the MOSFET gate, the SN75374 quad MOSFET driver should be used. PACKAGE OPTION ADDENDUM www.ti.com 19-Jun-2010 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) SN75372D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN75372DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN75372DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN75372DRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN75372DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN75372P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Contact TI Distributor or Sales Office SN75372PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Contact TI Distributor or Sales Office SN75372PSR ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN75372PSRE4 ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN75372PSRG4 ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. PACKAGE OPTION ADDENDUM www.ti.com 19-Jun-2010 Addendum-Page 2 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant SN75372DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SN75372PSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN75372DR SOIC D 8 2500 340.5 338.1 20.6 SN75372PSR SO PS 8 2000 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2012, Texas Instruments Incorporated SN75161B, SN75162B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS SLLS005B – OCTOBER 1980 – REVISED MAY 1995 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 Meets IEEE Standard 488-1978 (GPIB) 8-Channel Bidirectional Transceivers Power-Up/Power-Down Protection (Glitch Free) Designed to Implement Control Bus Interface SN75161B Designed for Single Controller SN75162B Designed for Multiple Controllers High-Speed, Low-Power Schottky Circuitry Low Power Dissipation . . . 72 mW Max Per Channel Fast Propagation Times . . . 22 ns Max High-Impedance pnp Inputs Receiver Hysteresis . . . 650 mV Typ Bus-Terminating Resistors Provided on Driver Outputs No Loading of Bus When Device Is Powered Down (VCC = 0) description The SN75161B and SN75162B eight-channel, general-purpose interface bus transceivers are monolithic, high-speed, low-power Schottky devices designed to meet the requirements of IEEE Standard 488-1978. Each transceiver is designed to provide the bus-management and data-transfer signals between operating units of a single- or multiple-controller instrumentation system. When combined with the SN75160B octal bus transceiver, the SN75161B or SN75162B provides the complete 16-wire interface for the IEEE-488 bus. The SN75161B and SN75162B feature eight driver-receiver pairs connected in a front-to-back configuration to form input/output (I/O) ports at both the bus and terminal sides. A powerup/- down disable circuit is included on all bus and receiver outputs. This provides glitch-free operation during VCC power up and power down. PRODUCTION DATA information is current as of publication date. Copyright W 1995, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SC TE REN IFC NDAC NRFD DAV EOI ATN SRQ NC GND 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 VCC NC REN IFC NDAC NRFD DAV EOI ATN SRQ NC DC (TOP VIEW) TE REN IFC NDAC NRFD DAV EOI ATN SRQ GND VCC REN IFC NDAC NRFD DAV EOI ATN SRQ DC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 GPIB I/O Ports Terminal I/O Ports (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 SC TE REN IFC NDAC NRFD DAV EOI ATN SRQ GND VCC NC REN IFC NDAC NRFD DAV EOI ATN SRQ DC (TOP VIEW) NC–No internal connection SN75161B . . . DW OR N PACKAGE SN75162B . . . DW PACKAGE SN75162B . . . N PACKAGE GPIB I/O Ports Terminal I/O Ports GPIB I/O Ports Terminal I/O Ports SN75161B, SN75162B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS SLLS005B – OCTOBER 1980 – REVISED MAY 1995 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description (continued) The direction of data through these driver-receiver pairs is determined by the DC, TE, and SC (on SN75162B) enable signals. The SC input on the SN75162B allows the REN and IFC transceivers to be controlled independently. The driver outputs (GPIB I/O ports) feature active bus-terminating resistor circuits designed to provide a high impedance to the bus when supply voltage VCC is 0. The drivers are designed to handle loads up to 48 mA of sink current. Each receiver features pnp transistor inputs for high input impedance and hysteresis of 400 mV for increased noise immunity. All receivers have 3-state outputs to present a high impedance to the terminal when disabled. The SN75161B and SN75162B are characterized for operation from 0°C to 70°C. Function Tables SN75161B RECEIVE/TRANSMIT CONTROLS BUS-MANAGEMENT CHANNELS DATA-TRANSFER CHANNELS DC TE ATN† ATN† SRQ REN IFC EOI DAV NDAC NRFD (Controlled by DC) (Controlled by TE) H H H R T R R T T R R H H L R L L H T R T T R R T T L L L T H L X R T R R R R T T L H X T R T T T T R R H = high level, L = low level, R = receive, T = transmit, X = irrelevant Direction of data transmission is from the terminal side to the bus side, and the direction of data receiving is from the bus side to the terminal side. Data transfer is noninverting in both directions. † ATN is a normal transceiver channel that functions additionally as an internal direction control or talk enable for EOI whenever the DC and TE inputs are in the same state. When DC and TE are in opposite states, the ATN channel functions as an independent transceiver only. SN75162B RECEIVE/TRANSMIT CONTROLS BUS-MANAGEMENT CHANNELS DATA-TRANSFER CHANNELS SC DC TE ATN† ATN† SRQ REN IFC EOI DAV NDAC NRFD (Controlled by DC) (Controlled by SC) (Controlled by TE) H H H R T T T R R H H L R L L H T R R R T T L L L T H L X R T R R T T L H X T R T T R R H T T L R R H = high level, L = low level, R = receive, T = transmit, X = irrelevant Direction of data transmission is from the terminal side to the bus side, and the direction of data receiving is from the bus side to the terminal side. Data transfer is noninverting in both directions. † ATN is a normal transceiver channel that functions additionally as an internal direction control or talk enable for EOI whenever the DC and TE inputs are in the same state. When DC and TE are in opposite states, the ATN channel functions as an independent transceiver only. SN75161B, SN75162B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS SLLS005B – OCTOBER 1980 – REVISED MAY 1995 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 CHANNEL-IDENTIFICATION TABLE NAME IDENTITY CLASS DC Direction Control TE Talk Enable Control SC System Control (SN75162B only) ATN Attention SRQ Service Request REN Remote Enable Bus IFC Interface Clear Management EOI End of Identity DAV Data Valid NDAC Not Data Accepted Data NRFD Not Ready for Data Transfer SN75161B logic symbol† EN3 1 ATN 8 1 ATN 13 1 1 EOI 7 3 EOI 14 1 3 SRQ 1 SRQ 12 1 1 REN 2 1 REN 19 1 1 IFC 3 1 IFC 18 1 1 DAV 6 2 DAV 15 1 2 NDAC 4 2 NDAC 17 1 2 2 1 16 NRFD 2 EN1/G4 EN2/G5 5 4 5 NRFD TE 1 DC 11 This symbol is in accordance with IEEE Std 91-1984 and IEC Publication 617-12. Designates 3-state outputs Designates passive-pullup outputs 9 SN75161B logic diagram (positive logic) NRFD 5 NRFD 16 NDAC 4 NDAC 17 DAV 6 DAV 15 IFC 3 IFC 18 REN 2 REN 19 SRQ 9 SRQ 12 EOI 7 EOI 14 11 DC 1 TE 13 ATN 8 ATN SN75161B, SN75162B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS SLLS005B – OCTOBER 1980 – REVISED MAY 1995 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75162B logic symbol† EN3 . 1 ATN 1 ATN 14 1 1 EOI 6 EOI 1 6 SRQ 1 SRQ 1 1 REN REN 1 3 IFC IFC 1 DAV 2 DAV 1 2 NDAC 2 NDAC 1 2 2 1 NRFD 2 EN1/G4 EN2/G5 5 4 NRFD TE DC This symbol is in accordance with IEEE Std 91-1984 and IEC Publication 617-12. Designates 3-state outputs Designates passive-pullup outputs EN3 12 2 1 15 SC 13 20 19 16 18 17 9 8 10 3 4 7 5 6 3 3 3 Pin numbers shown are for the N package. SN75162B logic diagram (positive logic) NRFD NRFD NDAC NDAC DAV DAV IFC IFC REN REN SRQ SRQ EOI EOI DC TE ATN ATN 12 2 1 14 15 13 20 19 16 18 17 9 8 10 3 4 7 5 6 SC SN75161B, SN75162B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS SLLS005B – OCTOBER 1980 – REVISED MAY 1995 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 schematics of inputs and outputs NOM 4 kW R(eq) 1.7 kW NOM 10 kW NOM VCC GND Input/Output Port Input/Output Port GND VCC NOM 10 kW NOM 4 kW NOM 1.7 kW NOM 9 kW GND Input VCC NOM 4 kW EQUIVALENT OF ALL CONTROL INPUTS TYPICAL OF SRQ, NDAC, AND NRFD GPIB I/O PORT Circuit inside dashed lines is on the driver outputs only. TYPICAL OF ALL I/O PORTS EXCEPT SRQ, NDAC, AND NRFD GPIB I/O PORTS Driver output R(eq) = 30 W NOM Receiver output R(eq) = 110 W NOM Circuit inside dashed lines is on the driver outputs only. R(eq) = equivalent resistor absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Low-level driver output current, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Lead temperature 1,6 mm (1/16) inch from the case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to network ground terminal. SN75161B, SN75162B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS SLLS005B – OCTOBER 1980 – REVISED MAY 1995 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DISSIPATION RATING TABLE PACKAGE TA 3 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING DW (20 pin) 1125 mW 9.0 mW/°C 720 mW DW (24 pin) 1350 mW 10.8 mW/°C 864 mW N (20 pin) 1150 mW 9.2 mW/°C 736 mW N (22 pin) 1700 mW 13.6 mW/°C 1088 mW recommended operating conditions MIN NOM MAX UNIT Supply voltage, VCC 4.75 5 5.25 V High-level input voltage, VIH 2 V Low-level input voltage, VIL 0.8 V High level output current IOH Bus ports with 3-state outputs –5.2 mA High-current, Terminal ports –800 mA Low level output current IOL Bus ports 48 Low-current, mA Terminal ports 16 Operating free-air temperature, TA 0 70 °C SN75161B, SN75162B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS SLLS005B – OCTOBER 1980 – REVISED MAY 1995 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VIK Input clamp voltage II = – 18 mA –0.8 –1.5 V Vhys Hysteresis voltage (VIT+ – VIT–) Bus See Figure 7 0.4 0.65 V VOH‡ High level output voltage Terminal IOH = – 800 mA 2.7 3.5 High-V Bus IOH = – 5.2 mA 2.5 3.3 VOL Low level output voltage Terminal IOL = 16 mA 0.3 0.5 Low-V Bus IOL = 48 mA 0.35 0.5 II Input current at maximum Terminal VI = 5 5 V 0 2 100 mA input voltage 5.5 0.2 IIH High-level input current Terminal and VI = 2.7 V 0.1 20 mA IIL Low-level input current control inputs VI = 0.5 V –10 –100 mA VI/O(b ) Voltage at bus port Driver disabled II(bus) = 0 2.5 3.0 3.7 bus) V II(bus) = – 12 mA –1.5 VI(bus) = – 1.5 V to 0.4 V –1.3 VI(bus) = 0.4 V to 2.5 V 0 –3.2 Power on Driver disabled VI(b ) = 2 5 V to 3 7 V 2.5 mA II/O(bus) Current into bus port bus) 2.5 3.7 –3.2 ( ) VI(bus) = 3.7 V to 5 V 0 2.5 VI(bus) = 5 V to 5.5 V 0.7 2.5 Power off VCC = 0, VI(bus) = 0 V to 2.5 V –40 mA IOS Short circuit output current Terminal –15 –35 –75 Short-mA Bus –25 –50 –125 ICC Supply current No load, TE, DE, and SC low 110 mA CI/O(b ) Bus port capacitance VCC = 5 V to 0, bus) Bus-CC 16 pF VI/O = 0 to 2 V, f = 1 MHz † All typical values are at VCC = 5 V, TA = 25°C. ‡ VOH applies for 3-state outputs only. SN75161B, SN75162B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS SLLS005B – OCTOBER 1980 – REVISED MAY 1995 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics, VCC = 5 V, CL = 15 pF, TA = 25°C (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay time, low- to high-level output Terminal Bus CL = 30 pF, 14 20 ns tPHL Propagation delay time, high- to low-level output L See Figure 1 14 20 tPLH Propagation delay time, low- to high-level output Terminal Bus (SRQ,NDAC, NRFD) CL = 30 pF, See Figure 1 29 35 ns tPLH Propagation delay time, low- to high-level output Bus Terminal CL = 30 pF, 10 20 ns tPHL Propagation delay time, high- to low-level output L See Figure 2 15 22 tPZH Output enable time to high level Bus (ATN 60 tPHZ Output disable time from high level TE,DC, ATN, EOI, REN, See Figure 3 45 ns tPZL Output enable time to low level or SC , , IFC, and 60 tPLZ Output disable time from low level DAV) 55 tPZH Output enable time to high level 55 tPHZ Output disable time from high level TE,DC, Terminal See Figure 4 50 ns tPZL Output enable time to low level or SC 45 tPLZ Output disable time from low level 55 SN75161B, SN75162B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS SLLS005B – OCTOBER 1980 – REVISED MAY 1995 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 PARAMETER MEASUREMENT INFORMATION VOLTAGE WAVEFORMS LOAD CIRCUIT 480 W 200 W (see Note A) CL = 30 pF Test Point 5 V Output Bus Input Terminal See Note B VOH VOH 0 V 3 V tPHL 2.2 V 1.0 V 1.5 V tPLH 1.5 V From (Bus) Output Under Test NOTES: A. CL includes probe and jig capacitance. B. The input pulse is supplied by a generator having the following characteristics: PRR 3 1 MHz, 50% duty cycle, tr 3 6 ns, tf 3 6 ns, ZO = 50 W. Figure 1. Terminal-to-Bus Load Circuit and Voltage Waveforms See Note B 1.5 V tPLH 1.5 V 1.5 V 1.5 V tPHL 3 V 0 V VOH VOL Bus Input Output From (Terminal) Output Under Test 4.3 V Test Point CL = 30 pF (see Note A) 240 W 3 kW LOAD CIRCUIT VOLTAGE WAVEFORMS Terminal NOTES: A. CL includes probe and jig capacitance. B. The input pulse is supplied by a generator having the following characteristics: PRR 3 1 MHz, 50% duty cycle, tr 3 6 ns, tf 3 6 ns, ZO = 50 W. Figure 2. Bus-to-Terminal Load Circuit and Voltage Waveforms SN75161B, SN75162B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS SLLS005B – OCTOBER 1980 – REVISED MAY 1995 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION NOTES: A. CL includes probe and jig capacitance. B. The input pulse is supplied by a generator having the following characteristics: PRR 3 1 MHz, 50% duty cycle, tr 3 6 ns, tf 3 6 ns, ZO = 50 W. S1 Open tPHZ 1.5 V 3 V 0 V S1 Closed 1 V 3.5 V VOL Input Control See Note B 1.5 V tPZH S1 VOLTAGE WAVEFORMS 2 V tPZL 90% 0.5 V tPLZ VOH 0 V Bus Output Bus Output 5 V Test Point CL = 15 pF (see Note A) 200 W 480 W LOAD CIRCUIT From (Bus) Output Under Test Figure 3. Bus Enable and Disable Times Load Circuit and Voltage Waveforms SN75161B, SN75162B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS SLLS005B – OCTOBER 1980 – REVISED MAY 1995 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 PARAMETER MEASUREMENT INFORMATION Output 90% Terminal S1 Open S1 Closed Terminal tPHZ VOLTAGE WAVEFORMS Output 0 V VOH tPLZ 0.7 V tPZL 1.5 V tPZH 1.5 V See Note B Control Input VOL 4 V 1 V 0 V 3 V 1.5 V LOAD CIRCUIT 3 kW 240 W Test Point S1 4.3 V CL = 15 pF (see Note A) From (Terminal) Output Under Test NOTES: A. CL includes probe and jig capacitance. B. The Input pulse is supplied by a generator having the following characteristics: PRR 3 1 MHz, 50% duty cycle, tr 3 6 ns, tf 3 6 ns, ZO = 50 W. Figure 4. Terminal Enable and Disable Times Load Circuit and Voltage Waveforms SN75161B, SN75162B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS SLLS005B – OCTOBER 1980 – REVISED MAY 1995 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS VOH – High-Level Output Voltage – V TERMINAL I/O PORTS HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 3.5 3 2.5 2 1.5 1 0.5 –5 –10 –15 –20 –25 –30 –35 0 –40 4 0 TA = 25°C VCC = 5 V IOH – High-Level Output Current – mA Figure 5 IOL – Low-Level Output Current – mA – Low-Level Output Voltage – V TERMINAL I/O PORTS LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT TA = 25°C VCC = 5 V 0.5 0.4 0.3 0.2 0.1 10 20 30 40 50 0 60 0.6 0 VOL Figure 6 2 – Output Voltage – V TERMINAL I/O PORTS OUTPUT VOLTAGE vs BUS INPUT VOLTAGE VIT– TA = 25°C No Load VCC = 5 V 3.5 3 2.5 2 1.5 1 0.5 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0 4 VI – Bus Input Voltage – V 0 VO VIT+ Figure 7 SN75161B, SN75162B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS SLLS005B – OCTOBER 1980 – REVISED MAY 1995 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TYPICAL CHARACTERISTICS IOH – High-Level Output Current – mA – High-Level Output Voltage – V GPIB I/O PORTS HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT TA = 25°C VCC = 5 V 3 2 1 –10 –20 –40 –30 –50 0 –60 0 0 VOH Figure 8 IOL – Low-Level Output Current – mA – Low-Level Output Voltage – V GPIB I/O PORTS LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT TA = 25°C VCC = 5 V 0.5 0.4 0.3 0.2 0.1 10 20 30 40 50 60 70 80 90 0 100 0.6 0 VOL Figure 9 Figure 10 VI – Input Voltage – V VO – Output Voltage – V GPIB I/O PORTS OUTPUT VOLTAGE vs THERMAL INPUT VOLTAGE TA = 25°C No Load VCC = 5 V 3 2 1 1 1.1 1.2 1.3 1.4 1.5 1.6 0 4 0.9 1.7 – Current – mA GPIB I/O PORTS CURRENT vs VOLTAGE 2 1 0 –1 –2 –3 –6 –1 0 1 2 3 4 5 –7 6 VI/O – Voltage – V –2 TA = 25°C VCC = 5 V ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ The Unshaded Area Conforms to Paragraph 3.5.3 of IEEE Standard 488-1978 II/O –5 –4 Figure 11 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) SN75161BDW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75161BDWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75161BDWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75161BDWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75161BDWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75161BN ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN75161BNE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN75162BDW ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75162BDWE4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75162BDWG4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75162BDWR ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75162BDWRE4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75162BDWRG4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75162BN OBSOLETE PDIP N 22 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 Addendum-Page 2 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant SN75161BDWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 SN75161BDWR SOIC DW 20 2000 330.0 24.4 10.8 13.1 2.65 12.0 24.0 Q1 SN75162BDWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Feb-2011 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN75161BDWR SOIC DW 20 2000 346.0 346.0 41.0 SN75161BDWR SOIC DW 20 2000 346.0 346.0 41.0 SN75162BDWR SOIC DW 24 2000 346.0 346.0 41.0 PACKAGE MATERIALS INFORMATION www.ti.com 19-Feb-2011 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Mobile Processors www.ti.com/omap Wireless Connectivity www.ti.com/wirelessconnectivity TI E2E Community Home Page e2e.ti.com Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2012, Texas Instruments Incorporated 6 O 6 (1.8639 V 2.1962 10 3.88 10 ) T 1481.96 u u GND NC V+ VO LMT88 LMT88 www.ti.com SNIS175 –MARCH 2013 LMT88 2.4V, 10μA, SC70, DSBGA Temperature Sensor Check for Samples: LMT88 1FEATURES DESCRIPTION The LMT88 is a precision analog output CMOS 2• Cost-Effective Alternative to Thermistors integrated-circuit temperature sensor that operates • Rated for full −55°C to +130°C range over a −55°C to 130°C temperature range. The • Available in an SC70 Package power supply operating range is 2.4 V to 5.5 V. The • Predictable Curvature Error transfer function of LMT88 is predominately linear, yet • Suitable for Remote Applications has a slight predictable parabolic curvature. The accuracy of the LMT88 when specified to a parabolic transfer function is ±1.5°C at an ambient temperature APPLICATIONS of 30°C. The temperature error increases linearly and • Industrial reaches a maximum of ±2.5°C at the temperature • HVAC range extremes. The temperature range is affected by the power supply voltage. At a power supply • Disk Drives voltage of 2.7 V to 5.5 V the temperature range • Automotive extremes are 130°C and −55°C. Decreasing the • Portable Medical Instruments power supply voltage to 2.4 V changes the negative extreme to −30°C, while the positive remains at • Computers 130°C. • Battery Management The LMT88 quiescent current is less than 10 μA. • Printers Therefore, self-heating is less than 0.02°C in still air. • Power Supply Modules Shutdown capability for the LMT88 is intrinsic • FAX Machines because its inherent low power consumption allows it to be powered directly from the output of many logic • Mobile Phones gates or does not necessitate shutdown at all. • Automotive The LMT88 is a cost-competitive alternative to thermistors. TYPICAL APPLICATION Full-Range Celsius (Centigrade) Temperature Sensor (−55°C TO 130°C) Operating From a Single LI-Ion Battery Cell space space VO = (−3.88×10−6×T2) + (−1.15×10−2×T) + 1.8639 space where: T is temperature, and VO is the measured output voltage of the LMT88. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2013, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. LMT88 GND NC V+ VO 1 4 3 5 GND 2 LMT88 SNIS175 –MARCH 2013 www.ti.com Figure 1. Output Voltage vs Temperature Table 1. Output Voltage vs Temperature TEMPERATURE (T) TYPICAL VO 130°C 303 mV 100°C 675 mV 80°C 919 mV 30°C 1515 mV 25°C 1574 mV 0°C 1863.9 mV –30°C 2205 mV −40°C 2318 mV −55°C 2485 mV CONNECTION DIAGRAMS GND (pin 2) may be grounded or left floating. For optimum thermal conductivity to the pc board ground plane, pin 2 must be grounded. NC (pin 1) must be left floating or grounded. Other signal traces must not be connected to this pin. Figure 2. SC70-5 Top View 2 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMT88 LMT88 www.ti.com SNIS175 –MARCH 2013 ABSOLUTE MAXIMUM RATINGS(1) VALUES Supply Voltage 6.5V to −0.2V Output Voltage (V+ + 0.6 V) to −0.6 V Output Current 10 mA Input Current at any pin (2) 5 mA Storage Temperature −65°C to 150°C Maximum Junction Temperature (TJMAX) 150°C Human Body Model 2500 V ESD Susceptibility (3) Machine Model 250 V Soldering process must comply with the Reflow Temperature Profile specifications. Refer to www.ti.com/packaging.(4) (1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For specified specifications and test conditions, see the ELECTRICAL CHARACTERISTICS. The specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. (2) When the input voltage (VI) at any pin exceeds power supplies (VI < GND or VI > V+), the current at that pin should be limited to 5 mA. (3) The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF capacitor discharged directly into each pin. (4) Reflow temperature profiles are different for lead-free and non-lead-free packages. OPERATION RATINGS Specified Temperature Range: TMIN ≤ TA ≤ TMAX LMT88 with 2.4 V ≤ V+≤ 2.7 V −30°C ≤ TA ≤ 130°C LMT88 with 2.7 V ≤ V+≤ 5.5 V −55°C ≤ TA ≤ 130°C Supply Voltage Range (V+) 2.4 V to 5.5 V Thermal Resistance, θJA (1) SC70 415°C/W (1) The junction to ambient thermal resistance (θJA) is specified without a heat sink in still air using the printed circuit board layout shown in PCB Layouts Used For Thermal Measurements. Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LMT88 LMT88 SNIS175 –MARCH 2013 www.ti.com ELECTRICAL CHARACTERISTICS Unless otherwise noted, these specifications apply for V+ = +2.7 VDC. Boldface limits apply for TA = TJ = TMIN to TMAX ; all other limits TA = TJ = 25°C; Unless otherwise noted. PARAMETER CONDITIONS TYPICAL(1) MAX(2) UNIT (Limit) TA = 25°C to 30°C ±1.5 ±4.0 °C (max) TA = 130°C ±5.0 °C (max) TA = 125°C ±5.0 °C (max) TA = 100°C ±4.7 °C (max) Temperature to Voltage Error TA = 85°C ±4.6 °C (max) VO = (−3.88×10−6×T2) + (−1.15×10−2×T) + 1.8639V(3) TA = 80°C ±4.5 °C (max) TA = 0°C ±4.4 °C (max) TA = –30°C ±4.7 °C (min) TA = –40°C ±4.8 °C (max) TA = –55°C ±5.0 °C (max) Output Voltage at 0°C 1.8639 V Variance from Curve ±1.0 °C Non-Linearity (4) –20°C ≤ TA ≤ 80°C ±0.4% Sensor Gain (Temperature Sensitivity or Average Slope) –30°C ≤ T −11.0 mV/°C (min) to equation: V A ≤ 100°C −11.77 O=−11.77 mV/ °C×T+1.860V −12.6 mV/°C (max) Output Impedance 0 μA ≤ IL ≤ 16 μA (5) (6) 160 Ω (max) Load Regulation(7) 0 μA ≤ IL ≤ 16 μA (5) (6) −2.5 mV (max) 2.4 V ≤ V+ ≤ 5.0V 3.7 mV/V (max) Line Regulation(8) 5.0 V ≤ V+ ≤ 5.5 V 11 mV (max) 2.4V ≤ V+ ≤ 5.0V 4.5 7 μA (max) Quiescent Current 5.0V ≤ V+ ≤ 5.5V 4.5 9 μA (max) 2.4V ≤ V+ ≤ 5.0V 4.5 10 μA (max) Change of Quiescent Current 2.4 V ≤ V+ ≤ 5.5V 0.7 μA Temperature Coefficient of Quiescent Current −11 nA/°C Shutdown Current V+ ≤ 0.8 V 0.02 μA (1) Typicals are at TJ = TA = 25°C and represent most likely parametric norm. (2) Limits are specified to TI's AOQL (Average Outgoing Quality Level). (3) Accuracy is defined as the error between the measured and calculated output voltage at the specified conditions of voltage, current, and temperature (expressed in°C). (4) Non-Linearity is defined as the deviation of the calculated output-voltage-versus-temperature curve from the best-fit straight line, over the temperature range specified. (5) Negative currents are flowing into the LMT88. Positive currents are flowing out of the LMT88. Using this convention the LMT88 can at most sink −1 μA and source 16 μA. (6) Load regulation or output impedance specifications apply over the supply voltage range of 2.4V to 5.5V. (7) Regulation is measured at constant junction temperature, using pulse testing with a low duty cycle. Changes in output due to heating effects can be computed by multiplying the internal dissipation by the thermal resistance. (8) Line regulation is calculated by subtracting the output voltage at the highest supply input voltage from the output voltage at the lowest supply input voltage. 4 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMT88 6 O 6 (1.8639 V 2.1962 10 3.88 10 T 1481.96 u u LMT88 www.ti.com SNIS175 –MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS PCB Layouts Used For Thermal Measurements Figure 4. Layout Used For No Heat Sink Measurements Figure 5. Layout Used For Measurements With Small Heat Sink LMT88 TRANSFER FUNCTION The LMT88 transfer function can be described in different ways with varying levels of precision. A simple linear transfer function, with good accuracy near 25°C, is VO = −11.69 mV/°C × T + 1.8663 V (1) Over the full operating temperature range of −55°C to 130°C, best accuracy can be obtained by using the parabolic transfer function. VO = (−3.88×10−6×T2) + (−1.15×10−2×T) + 1.8639 (2) solving for T: (3) A linear transfer function can be used over a limited temperature range by calculating a slope and offset that give best results over that range. A linear transfer function can be calculated from the parabolic transfer function of the LMT88. The slope of the linear transfer function can be calculated using the following equation: m = −7.76 × 10−6× T − 0.0115, (4) where T is the middle of the temperature range of interest and m is in V/°C. For example for the temperature range of TMIN = −30 to TMAX = +100°C: T = 35°C (5) and m = −11.77 mV/°C (6) The offset of the linear transfer function can be calculated using the following equation: b = (VOP(TMAX) + VOP(T) − m × (TMAX+T))/2 (7) where: VOP(TMAX) is the calculated output voltage at TMAX using the parabolic transfer function for VO VOP(T) is the calculated output voltage at T using the parabolic transfer function for VO. Using this procedure the best fit linear transfer function for many popular temperature ranges was calculated in Table 2. As shown in Table 2 the error that is introduced by the linear transfer function increases with wider temperature ranges. Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LMT88 LMT88 SNIS175 –MARCH 2013 www.ti.com Table 2. First Order Equations Optimized for Different Temperature Ranges TEMPERATURE RANGE MAXIMUM DEVIATION OF LINEAR EQUATION LINEAR EQUATION Tmin (°C) Tmax (°C) FROM PARABOLIC EQUATION (°C) −55 130 VO = −11.79 mV/°C × T + 1.8528 V ±1.41 −40 110 VO = −11.77 mV/°C × T + 1.8577 V ±0.93 −30 100 VO = −11.77 mV/°C × T + 1.8605 V ±0.70 -40 85 VO = −11.67 mV/°C × T + 1.8583 V ±0.65 −10 65 VO = −11.71 mV/°C × T + 1.8641 V ±0.23 35 45 VO = −11.81 mV/°C × T + 1.8701 V ±0.004 20 30 VO = –11.69 mV/°C × T + 1.8663 V ±0.004 MOUNTING The LMT88 can be applied easily in the same way as other integrated-circuit temperature sensors. It can be glued or cemented to a surface. The temperature that the LMT88 is sensing will be within about +0.02°C of the surface temperature to which the LMT88's leads are attached to. This presumes that the ambient air temperature is almost the same as the surface temperature; if the air temperature were much higher or lower than the surface temperature, the actual temperature measured would be at an intermediate temperature between the surface temperature and the air temperature. To ensure good thermal conductivity the backside of the LMT88 die is directly attached to the pin 2 GND pin. The tempertures of the lands and traces to the other leads of the LMT88 will also affect the temperature that is being sensed. Alternatively, the LMT88 can be mounted inside a sealed-end metal tube, and can then be dipped into a bath or screwed into a threaded hole in a tank. As with any IC, the LMT88 and accompanying wiring and circuits must be kept insulated and dry, to avoid leakage and corrosion. This is especially true if the circuit may operate at cold temperatures where condensation can occur. Printed-circuit coatings and varnishes such as Humiseal and epoxy paints or dips are often used to ensure that moisture cannot corrode the LMT88 or its connections. The thermal resistance junction to ambient (θJA) is the parameter used to calculate the rise of a device junction temperature due to its power dissipation. For the LMT88 the equation used to calculate the rise in the die temperature is as follows: TJ = TA + θJA [(V+ IQ) + (V+ − VO) IL] where IQ is the quiescent current and ILis the load current on the output. Since the LMT88's junction temperature is the actual temperature being measured care should be taken to minimize the load current that the LMT88 is required to drive. 6 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMT88 OUT Heavy Capacitive Load, Wiring, Etc. LMT88 + d R C OUT Heavy Capacitive Load, Wiring, Etc. LMT88 + d R C 0.1 μF Bypass Optional 0.1 μF Bypass Optional OUT Heavy Capacitive Load, Wiring, Etc. LMT88 + d To A High-Impedance Load LMT88 www.ti.com SNIS175 –MARCH 2013 The tables shown in Table 3 summarize the rise in die temperature of the LMT88 without any loading, and the thermal resistance for different conditions. Table 3. Temperature Rise of LMT88 Due to Self-Heating and Thermal Resistance (θJA)(1) SC70-5 SC70-5 NO HEAT SINK SMALL HEAT SINK θJA TJ − TA θJA TJ − TA (°C/W) (°C) (°C/W) (°C) Still air 412 0.2 350 0.19 Moving air 312 0.17 266 0.15 (1) See PCB Layouts Used For Thermal Measurements for PCB layout samples. CAPACITIVE LOADS The LMT88 handles capacitive loading well. Without any precautions, the LMT88 can drive any capacitive load less than 300 pF as shown in Figure 6. Over the specified temperature range the LMT88 has a maximum output impedance of 160 Ω. In an extremely noisy environment it may be necessary to add some filtering to minimize noise pickup. It is recommended that 0.1 μF be added from V+ to GND to bypass the power supply voltage, as shown in . In a noisy environment it may even be necessary to add a capacitor from the output to ground with a series resistor as shown in . A 1 μF output capacitor with the 160 Ω maximum output impedance and a 200 Ω series resistor will form a 442 Hz lowpass filter. Since the thermal time constant of the LMT88 is much slower, the overall response time of the LMT88 will not be significantly affected. Figure 6. LMT88 No Decoupling Required for Capacitive Loads Less Than 300 pF R (Ω) C (μF) 200 1 470 0.1 680 0.01 1 k 0.001 spacer between the table and graphic Figure 7. LMT88 with Filter for Noisy Environment and Capacitive Loading Greater Than 300 pF Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LMT88 GND 0.1 PF V+ VO LMT88 GND NC 0.1 PF V+ (+5.0V) 1 k ADCV0831 LM4040BIM3-4.1 GND VIN V+ 6 5 4 1 3 2 3 2 1 4 5 CS DO CLK 470 LMT88 SHUTDOWN +VS VO Any logic device output 4.1V R1 R3 R2 LM4040 U3 0.1 PF R4 VOUT V+ VT VTemp + - U1 V+ LMT88 U2 (High = overtemp alarm) VT1 VT2 VTEMP VOUT VT1 = R1 + R2||R3 (4.1)R2 VT2 = R2 + R1||R3 (4.1)R2||R3 LM7211 LMT88 SNIS175 –MARCH 2013 www.ti.com NOTE Either placement of resistor as shown above is just as effective. APPLICATION CIRCUITS Figure 8. Centigrade Thermostat Figure 9. Conserving Power Dissipation with Shutdown Figure 10. Suggested Connection to a Sampling Analog to Digital Converter Input Stage Most CMOS ADCs found in ASICs have a sampled data comparator input structure that is notorious for causing grief to analog output devices such as the LMT88 and many op amps. The cause of this grief is the requirement of instantaneous charge of the input sampling capacitor in the ADC. This requirement is easily accommodated by the addition of a capacitor. Since not all ADCs have identical input stages, the charge requirements will vary necessitating a different value of compensating capacitor. This ADC is shown as an example only. If a digital output temperature is required please refer to devices such as the LM74. 8 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMT88 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples LMT88DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -55 to 130 T9C LMT88DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -55 to 130 T9C (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. 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TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant LMT88DCKR SC70 DCK 5 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 LMT88DCKT SC70 DCK 5 250 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMT88DCKR SC70 DCK 5 3000 210.0 185.0 35.0 LMT88DCKT SC70 DCK 5 250 210.0 185.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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As such, the goods being provided may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety measures typically found in the end product incorporating the goods. As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic compatibility and therefore may not meet the technical requirements of the directive. Should this evaluation kit not meet the specifications indicated in the EVM User’s Guide, the kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims arising from the handling or use of the goods. Please be aware that the products received may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). Due to the open construction of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic discharge. EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES. TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive. TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Please read the EVM User’s Guide and, specifically, the EVM Warnings and Restrictions notice in the EVM User’s Guide prior to handling the product. This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact the TI application engineer. Persons handling the product must have electronics training and observe good laboratory practice standards. No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or combination in which such TI products or services might be or are used. Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2002, Texas Instruments Incorporated EVM WARNINGS AND RESTRICTIONS It is important to operate this EVM within the supply voltage range of 3 V to 3.6 V. Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the supply range, please contact a TI field representative prior to connecting the input power. Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM. Please consult the EVM User’s Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative. During normal operation, some circuit components may have case temperatures greater than 125°C. The EVM is designed to operate properly with certain components above 125°C as long as the input and output ranges are maintained. These components include but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of devices can be identified using the EVM schematic located in the EVM User’s Guide. When placing measurement probes near these devices during operation, please be aware that these devices may be very warm to the touch. Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2002, Texas Instruments Incorporated Information About Cautions and Warnings v Preface Read This First About This Manual This EVM user’s guide provides information about the 2-GBPS differential repeater evaluation module. How to Use This Manual This document contains the following chapters: Chapter 1 — Introduction Chapter2 — Setup and Equipment Required Chapter 3 — EVM Construction Information About Cautions and Warnings This book may contain cautions and warnings. This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software or equipment. This is an example of a warning statement. A warning statement describes a situation that could potentially cause harm to you. The information in a caution or a warning is provided for your protection. Please read each caution and warning carefully. Related Documentation From Texas Instruments vi Related Documentation From Texas Instruments To obtain a copy of any of the following TI document, call the Texas Instruments Literature Response Center at (800) 477-8924 or the Product Information Center (PIC) at (972) 644-5580. When ordering, identify this booklet by its title and literature number. Updated documents can also be obtained through our website at www.ti.com. Data Sheet: Literature Number: SN65LVDS100/101 SLLS516 SN65CML100 SLLS547 FCC Warning This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference. Contents vii Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Signal Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 2 Setup and Equipment Required . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Applying an Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.3 Observing an Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.4 Typical Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 3 EVM Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.3 Board Stackup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.4 Board Layer Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Figures 1-1 EVM With SN65LVDS100 Installed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1-2 Schematic of EVM Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 2-1 TIA/EIA-644-A LVDS Driver Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2-2 EVM Power Connections for SN65LVDS100 Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2-3 External Termination for Differential CML or LVPECL Inputs to EVM . . . . . . . . . . . . . . . . . 2-4 2-4 External Termination for Single-Ended LVPECL Inputs to EVM . . . . . . . . . . . . . . . . . . . . . . 2-5 2-5 Typical Output From SN65LVDS100 EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Tables 1-1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Contents viii Introduction 1-1 Introduction The 2-GBPS differential repeater evaluation module (EVM) allows evaluation of the SN65LVDS100, SN65LVDS101, and SN65CML100 differential repeaters/ translators. This user’s guide gives a brief overview of the EVM, setup and operation instructions, and typical test results that can be expected. Topic Page 1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Signal Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Chapter 1 Overview 1-2 1.1 Overview The 2-GBPS differential repeater evaluation module (EVM) is designed for evaluation of the SN65LVDS100, SN65LVDS101, and SN65CML100 differential repeaters/ translators. The SN65LVDS100 and SN65LVDS101 devices both incorporate wide common-mode range receivers, allowing receipt of LVDS, LVPECL, or CML input signals. The SN65LVDS100 provides an LVDS output, the SN65LVDS101 incorporates an LVPECL output driver, and the SN65CML100 delivers a CML output. Both devices provide a VBB reference voltage to support receiving of single-ended LVPECL input signals, or biasing of ac-coupled inputs. The EVM can be ordered with the SN65LVDS100, SN65LVDS101, or SN65CML100 installed. Orderable EVM part numbers are shown in Table 1-1. Table 1-1. Ordering Information EVM Part Number Installed Device SN65LVDS100EVM SN65LVDS100DGK SN65LVDS101EVM SN65LVDS101DGK SN65CML100EVM SN65CML100DGK Detailed information relating to the SN65LVDS100, SN65LVDS101, and SN65CML100 can be found in the device data sheet, a copy of which is shipped as part of the EVM or available from www.ti.com. A picture of the EVM, with an SN65LVDS100 device installed, is shown in Figure 1-1. Figure 1-1. EVM With SN65LVDS100 Installed Signal Paths Introduction 1-3 1.2 Signal Paths A partial schematic of the EVM is shown in Figure 1-2 and a full schematic is in chapter 3. Edge-mount SMA connectors (J4, J5, J6, and J7) are provided for data input and output connections. Three power jacks (J1, J2, and J3) are used to provide power to and a ground reference, for the EVM. The use of these power jacks is addressed later. Chapter 3 also provides a parts list for the EVM, as well as an indication of which components are installed when shipped. Figure 1-2. Schematic of EVM Signal Path NC A B Vbb VCC Y Z GND R5 Uninstalled JMP2 1 2 C12 .010 μF DUT_MSOP8 DUT1 VCC01 VCC C11 .010 μF R2 Uninstalled J6 GND J7 GND R4 Uninstalled R3 Uninstalled J4 R1 100 Ω GND J5 GND 1 1 1 2 3 4 8 7 6 5 1 1 1-4 Setup and Equipment Required 2-1 Setup and Equipment Required This chapter examines the setup and use of the evaluation module and the results of operation. Topic Page 2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Applying an Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.3 Observing an Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.4 Typical Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Chapter 2 Overview 2-2 2.1 Overview LVDS driver output characteristics are specified in the TIA/EIA-644 standard. LVDS drivers nominally provide a 350-mV differential signal, with a 1.25-V offset from ground. These levels are attained when driving a 100-Ω differential line-termination test load (see Figure 2-1). In real applications, there may be a ground potential between a driver and receiver(s). The driver must drive the common-mode load presented by the receiver inputs and the differential load. A TIA/EIA-644-A compliant LVDS driver is required to maintain its differential output with up to 32 standard receivers. The receiver load is represented by the 3.74-kΩ resistors shown in Figure 2-1. Figure 2-1. TIA/EIA-644-A LVDS Driver Test Load _ + A B VOD 100 Ω 3.74 kΩ 3.74 kΩ 0 V ≤ Vtest ≤ 2.4 V D LVPECL drivers are generally loaded with 50-Ω resistors to a termination bias voltage, VT. VT is usually 2-V below the supply voltage of the driver circuit. When the driver operates from a 3.3-V supply, VT is set to approximately 1.3 V. CML drivers are generally loaded with 50-Ω resistors to a termination voltage, VTT. VTT can either be equivalent to the supply voltage of the driver circuit (equal to VCC) or set to 2.5 V or 1.8 V, irrelevant to the supply voltage. If desired, the SN65CML100 can be configured to drive a dual 50-Ω load. In this configuration one 50-Ω resistor (tied to the termination voltage VTT) is placed near the output of the SN65CML100 and a second 50-Ω resistor (also tied to VTT) is placed near the end of the transmission line. The EVM has been designed to support the SN65LVDS100 LVDS-output device, the SN65LVDS101 LVPECL-output device, and the SN65CML100 CML-output device. By using the three power jacks (J1, J2, and J3), as well as installing termination resistors (R2, R3, and R4), different methods of termination and probing can be used to evaluate the device output characteristics. The typical setup for the SN65LVDS100 is shown in Figure 2-2. Applying an Input Setup and Equipment Required 2-3 Figure 2-2. EVM Power Connections for SN65LVDS100 Evaluation Pattern Generator Oscilloscope EVM Power Supply 1 + - Power Supply 2 + - EVM VCC GND DUT GND 1.22V 3.3V Matched Cables SMA to SMA Matched Cables SMA to SMA J2 J7 J6 J5 J4 J3 J1 100 Ω 50 Ω 50 Ω Warning Power jacks J1, J2, and J3 are not insulated on the backside of the EVM. Place on a nonconductive surface. 2.2 Applying an Input LVDS inputs should be applied to SMA connectors J4 and J5, while keeping R1 installed. The EVM comes with a 100-Ω termination resistor (R1) installed across the differential inputs. This 100-Ω resistor represents an LVDS termination. When using a general-purpose signal generator with 50-Ω output impedance, make sure that the signal levels are between 0 V to 4 V with respect to J3. A signal generator such as the Advantest D3186 can simulate LVDS, LVPECL, or CML inputs. When using LVPECL or CML drivers for the input signal, termination external to the EVM must be provided (see Figure 2-3). LVPECL drivers should be terminated with 50-Ω pulldowns to VT, while CML drivers should be terminated Applying an Input 2-4 with 50-Ω pullups to VTT. When using external terminations, the onboard termination resistor R1 should be removed from the EVM. It should be noted that the signal quality at the receiver input may be degraded when external terminations are used, as a significant stub exists from the external termination network to the receiver input. The user needs to verify that the transition time of the input signal, coupled with the stub length, does not lead to reflection problems. These concerns would be addressed in a real application where the terminations are placed close to the receiver input. Figure 2-3. External Termination for Differential CML or LVPECL Inputs to EVM Select VT for LVPECL or Select VTT for CML Select VT for LVPECL or Select VTT for CML 50 Ω 50 Ω OUT OUT Signal Source EVM BOARD NOTES: A. Locate 50-Ω resistors as close to the EVM as possible B. Remove R1 A B Y Z Finally, as mentioned above, the SN65LVDS100, SN65LVDS101, and SN65CML100 devices provide a VBB reference voltage output. This output can be used with an externally terminated, single-ended, LVPECL input to convert from a single-ended input to a differential output. The same cautions that are mentioned above concerning signal quality and reflections apply. When using VBB as a single-ended reference, R1 should be removed while R5 and JMP2 should be installed. The single-ended input signal is applied to J4. This setup directly connects the VBB output to the DUT receiver B input via a 0-Ω connection (see Figure 2-4). Observing an Output Setup and Equipment Required 2-5 Figure 2-4. External Termination for Single-Ended LVPECL Inputs to EVM 50 Ω OUT Signal Source EVM BOARD NOTES: A. Add jumper Jmp2 and 0-Ω R5 B. Remove R1 A B Y Z 2.3 Observing an Output Direct connection to an oscilloscope with 50-Ω internal terminations to ground is accomplished without R2, R3, and R41. The outputs are available at J6 and J7 for direct connection to oscilloscope inputs. Matched length cables must be used when connecting the EVM to a scope to avoid inducing skew between the noninverting (+) and inverting (-) outputs. The three power jacks (J1, J2, and J3) are used to provide power and a ground reference for the EVM. The power connections to the EVM determine the common-mode load to the device. As mentioned earlier, LVDS drivers have limited common-mode driver capability. When connecting the EVM outputs directly to oscilloscope inputs, setting of the oscilloscope common-mode offset voltage is required, as the oscilloscope presents low common-mode load impedance to the device. Returning to Figure 2-2, power supply 1 is used to provide the required 3.3 V to the EVM. Power supply 2 is used to offset the EVM ground relative to the DUT ground. The EVM ground is connected to the oscilloscope ground through the returns on SMA connectors J6 and J7. With power applied as shown in Figure 2-2, the common-mode voltage seen by the SN65LVDS100 is approximately equal to the reference voltage being used inside the device preventing significant common-mode current to flow. Optimum device setup can be confirmed by adjusting the voltage on power supply 2 until its current is minimized. It is important to note that use of the dual supplies and offsetting the EVM ground relative to the DUT ground are simply steps needed for the test and evaluation of devices. Actual designs would include high-impedance receivers, which would not require the setup steps outlined above. 1 As delivered R2, R3, and R4 are not installed Typical Test Results 2-6 LVPECL drivers need a 50-Ω termination to VT. A modification of Figure 2-2 and the above instructions are used when evaluating an SN65LVDS101 with a direct connection to a 50-Ω oscilloscope. With power supply 1 in Figure 2-2 set to 3.3 V, power supply 2 should be set to 1.3 V (2 V below VCC) to provide the correct termination voltage. CML drivers need a 50-Ω termination to VTT (VTT is either VCC, 2.5 V, or 1.8 V). A modification of Figure 2-2 and the instructions for the SN65LVDS100 are used when evaluating a SN65CML100 with direct connection to a 50-Ω oscilloscope. With power supply 1 in Figure 2-2 set to 3.3 V, power supply 2 should be set to either VCC (3.3 V), 2.5 V, or 1.8 V to provide the correct termination voltage. Dual termination of the output can be achieved by placing 49.9-Ω resistors at R2 and R3 and connecting to an oscilloscope as described above. If the EVM outputs are to be evaluated with a high-impedance probe, direct probing on the EVM is supported via installation of R2, R3, and R4. LVDS outputs can be observed by installing R4, a 100-Ω resistor. LVPECL outputs can be observed by installing R2 and R3 (49.9-Ω resistors), and setting power supply 2 to 1.3 V. CML outputs can be observed by setting power supply 2 to VTT and installing 49.9-Ω resistors at R2 and R3 for single termination, or 24.9-Ω resistors at R2 and R3 for dual termination (Note that power supply 2 must be able to sink current.) 2.4 Typical Test Results Figure 2-5 shows a typical test result obtained with the EVM. Figure 2-5 shows the output of an SN65LVDS100 being driven directly into a 50-Ω oscilloscope. For this figure, the SN65LVDS100 was stimulated with an HP 3-GBPS BERT. The input data was pseudorandom data at 2 GBPS and with a random record length of 223-1. The BERT drove two electrically matched one-meter cables with an electrical length of 3.667 ns. These cables were then connected to the EVM inputs. The EVM outputs were connected through another set of electrically matched one-meter cables and terminated by a TDS8000 oscilloscope’s 50-Ω resistors to ground. Typical Test Results Setup and Equipment Required 2-7 Figure 2-5. Typical Output From SN65LVDS100 EVM 2-8 EVM Construction 3-1 EVM Construction This chapter lists the EVM components and examines the construction of the evaluation module. Topic Page 3.1 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.3 Board Stackup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.4 Board Layer Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Chapter 3 Schematic 3-2 3.1 Schematic NC A B Vbb VCC Y Z GND R5 Uninstalled JMP2 1 2 C12 .010 μF DUT_MSOP8 DUT1 VCC01 VCC C11 .010 μF R2 Uninstalled J6 GND J7 GND R4 Uninstalled R3 Uninstalled J4 R1 100 Ω GND J5 GND 1 1 1 2 3 4 8 7 6 5 1 1 VCC VCC01 + + + + C1 10 μF C6 10 μF C2 68 μF C7 68 μF C3 1 μF C8 1 μF C4 0.1 μF C9 0.1 μF C5 0.001 μF 109 0.001 μF J1 -1 J2 -1 J3 -1 MNTH1 MNTH2 MNTH3 MNTH4 Bill of Materials EVM Construction 3-3 3.2 Bill of Materials ITEM QTY MFG MFG PART NO. REF. DES. DESCRIPTION VALUE OR FUNCTION NOT INSTALLED 1 2 Sprague 293D106X0035D2W C1,C6 Capacitor, SMT, TANT 35 V, 10%, 10 μF 2 2 AVX 12063G105ZATRA C3,C8 Capacitor, SMT1206 25 V, 80 -20%, 1.0 μF 3 2 AVX 12065C104JATMA C4,C9 Capacitor, SMT1206 50 V, 5%, 0.1 μF 4 2 Sprague 592D686X0010R2T C2,C7 Capacitor, SMT, TANT 10 V, 20%, 68 μF, Low ESR 5 2 Murata GRM39X7R103K50V C11, C12 Capacitor, SMT0603 50 V,±10%, 0.010 μF 6 2 AVX 06033G102JATMA C5,C10 Capacitor, SMT0603 25 V, 5%, 0.001 μF 7 3 ITT-Pomona 3267 J1, J2, J3 Connector, banana jack Bannana jack 8 4 EF Johnson 142-0701-801 J4, J5, J6, J7 Connector SMA Jack, end launch, 0.062 9 1 Dale CRCW0603100F R1 Resistor, SMT,0603 100 Ω 10 2 R2, R3 Resistor, SMT, 0603 49.9 Ω R2, R3 11 1 R4 Resistor, SMT, 0603 100 Ω R4 12 1 R5 Resistor, SMT, 0603 0 Ω R5 13 1 AMP 4-103239-0x2 JMP2 Header Male, 2 pin, 0.100 CC 14 1 TI SN65LVDS100† SN65LVDS101† DUT1 IC, SMT, 8P 2-GBPS differential repeater/translator 15 3 Screws 16 3 Nuts 17 1 User’s manual 18 1 Data sheet † Only one is installed Board Stackup 3-4 3.3 Board Stackup 9 Copper Foil CH A1 Copper Foil CH A1 .0062 PREPREG .0062 PREPREG CORE .015 C1/0 A1 .0122 PREPREG CORE .015 C0/1 A1 SECTION A - A NO SCALE TOP SIDE-SIGNAL/GND FILL (LAYER 1) INT1-GND PLANE (LAYER 2) INT2-VCC SPLIT PLANE (LAYER 3) 9 BOTTOM SIDE-GND PLANE (LAYER 4) Symbol Diameter (in) 0.0160 0.0320 0.0400 0.0500 0.1250 0.2720 Plated Yes Yes Yes Yes Yes Yes Quantity 49 82343 Through Holes 3.000 A A 3.000 DATUM 0,0 TOP SIDE SHOWN DRILL 0.250 0.250 NN THIS IS AN IMPEDANCE CONTROLLED BOARD. GENERAL NOTES: UNLESS OTHERWISE SPECIFIED 1. ALL FABRICATION ITEMS MUST MEET OR EXCEED BEST INDUSTRY PRACTICE. IPC-A 600C ( Commercial Std.) 2.LAMINATE MATERIAL: NELCO N4000-13 (DO NOT USE - 13SI) 3. COOPER WEIGHT:1 OZ. START INTERNAL AND 1/2 OZ. START EXTERNAL 4. FINISHED BOARD THICKNESS: .062 ±10% 5. MAXIMUM WARP AND TWIST TO BE .005 INCH PER INCH 6 MINIMUM COPPER WALL THICKNESS OF PLATED-THRU HOLES TO BE .001 INCH 7 MINIMUM ANNULAR RING OF PLATED-THRU HOLES TO BE .002 INCH 8. MINIMUM ALLOWABLE LINE REDUCTION TO BE 20% OR .002 WHICHEVER IS GREATER 9. 0.013 INCH SIGNAL LINES ON LAYER 1 TO BE IMPEDANCE CONTROLLED 50 OHMS TO GND ±10% 0.010 INCH SIGNAL LINES ON LAYER 1 TO BE IMPEDANCE CONTROLLED 100 OHMS TO EACH OTHER ±10% 10. DIELECTRIC CONSTANTS ARE: CORE: 3.2 PREPREG:3.2 PROCESS NOTES: 1. CIRCUITRY ON OUTER LAYERS TO BE PLATED WITH TIN LEAD 2. SOLDERMASK BOTH SIDES PER ARTWORK: GREEN LPI 3. SILKSCREEN BOTH SIDE PER ARTWORK: COLOR=WHITE 4 N 6434666A PWA, BENCH, EVALUATION BOARD, SN65LVDS100/101D, EVM 10/31/01 Board Layer Patterns EVM Construction 3-5 3.4 Board Layer Patterns (Not to Scale) Layer 1 - Signal/GND Fill (Top Side) Layer 2 - GND Plane (INT1) Board Layer Patterns 3-6 Layer 3 - VCC Split Plane (INT2) Layer 4 - GND Plane (Bottom Side) ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Piccolo Microcontrollers Check for Samples: TMS320F28055, TMS320F28054, TMS320F28053, TMS320F28052, TMS320F28051, TMS320F28050 1 TMS320F2805x ( Piccolo™) MCUs 1.1 Features 123 • Highlights • Programmable Control Law Accelerator (CLA) – High-Efficiency 32-Bit CPU ( TMS320C28x™) – 32-Bit Floating-Point Math Accelerator – 60-MHz Device – Executes Code Independently of the Main – Single 3.3-V Supply CPU – Integrated Power-on and Brown-out Resets • Low Device and System Cost: – Two Internal Zero-pin Oscillators – Single 3.3-V Supply – Up to 42 Multiplexed GPIO Pins – No Power Sequencing Requirement – Three 32-Bit CPU Timers – Integrated Power-on Reset and Brown-out – On-Chip Flash, SARAM, Message RAM, OTP, Reset CLA Data ROM, Boot ROM, Secure ROM – Low Power Memory – No Analog Support Pins – Dual-Zone Security Module • Clocking: – Serial Port Peripherals (SCI/SPI/I2C/eCAN) – Two Internal Zero-pin Oscillators – Enhanced Control Peripherals – On-Chip Crystal Oscillator/External Clock • Enhanced Pulse Width Modulator (ePWM) Input • Enhanced Capture (eCAP) – Dynamic PLL Ratio Changes Supported • Enhanced Quadrature Encoder Pulse – Watchdog Timer Module (eQEP) – Missing Clock Detection Circuitry – Analog Peripherals • Up to 42 Individually Programmable, • One 12-Bit Analog-to-Digital Converter Multiplexed GPIO Pins With Input Filtering (ADC) • Peripheral Interrupt Expansion (PIE) Block That • One On-Chip Temperature Sensor Supports All Peripheral Interrupts • Up to Seven Comparators With up to • Three 32-Bit CPU Timers Three Integrated Digital-to-Analog • Independent 16-Bit Timer in Each ePWM Converters (DACs) Module • One Buffered Reference DAC • On-Chip Memory • Up to Four Programmable Gain – Flash, SARAM, Message RAM, OTP, CLA Amplifiers (PGAs) Data ROM, Boot ROM, Secure ROM Available • Up to Four Digital Filters • 128-Bit Security Key and Lock – 80-Pin Package – Protects Secure Memory Blocks • High-Efficiency 32-Bit CPU ( TMS320C28x™) – Prevents Firmware Reverse Engineering – 60 MHz (16.67-ns Cycle Time) • Serial Port Peripherals – 16 x 16 and 32 x 32 MAC Operations – Three SCI (UART) Modules – 16 x 16 Dual MAC – One SPI Module – Harvard Bus Architecture – One Inter-Integrated-Circuit (I2C) Bus – Atomic Operations – One Enhanced Controller Area Network – Fast Interrupt Response and Processing (eCAN) Bus – Unified Memory Programming Model • Advanced Emulation Features – Code-Efficient (in C/C++ and Assembly) – Analysis and Breakpoint Functions • Endianness: Little Endian – Real-Time Debug via Hardware • 80-Pin PN Low-Profile Quad Flatpack (LQFP) 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2Piccolo, TMS320C28x, C28x, TMS320C2000, Code Composer Studio, XDS510, XDS560 are trademarks of Texas Instruments. 3All other trademarks are the property of their respective owners. ADVANCE INFORMATION concerns new products in the sampling or preproduction Copyright © 2012, Texas Instruments In